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Partial File Text QL3040 / QL3040R 40,000 Usable PLD Gate pASICÂ®3 FPGA Combining High Performance and High Density PRELIMINARY DATA pASIC 3 HIGHLIGHTS ... 40,000 usable PLD gates, 252 I/O pins 20,736 bit
Datasheet Type Scan
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown

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