DSAIHSC00038546.pdf by Not Available

Partial File Text QL3025 / QL3025R 25,000 Usable PLD Gate pASICÂ®3 FPGA Combining High Performance and High Density PRELIMINARY DATA ... 25,000 usable PLD gates, 204 I/O pins 16,128 bit RAM Option S High
Datasheet Type Scan
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown

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