DSASW00325978.pdf by PhaseLink

Partial File Text PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) DIE CONFIGURATION FEATURES DIE SPECIFICATIONS OESEL^ VDD VDD VDD VDD N/C Reserved Reserved 23 2
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a2020 C502A clock ma 1042 P620-30DC PLL620-30 PLL620-30DC