74LVC109DB,118 datasheet by NXP Semiconductors

Description Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; F<sub>max</sub>: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13"
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
Price & Stock
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74LVC109DB,118 datasheet preview Download Datasheet