74HCT112D,653 datasheet
by NXP Semiconductors
- dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; F<sub>max</sub>: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC
- Original
- Yes
- Unknown
- Transferred
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