74HC73PW,118 datasheet by NXP Semiconductors

Description Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; F<sub>max</sub>: 77 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT402-1 (TSSOP14); Container: Reel Pack, SMD, 13"
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Transferred
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74HC73PW,118 datasheet preview Download Datasheet