74ABT899D,118 datasheet by NXP Semiconductors

Description 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) - Description: Latched Transceiver with Parity Generator/Checker (3-State) ; Logic switching levels: TTL ; Number of pins: 28 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.2 ns; Voltage: 4.5-5.5 V; Package: SOT136-1 (SO28); Container: Reel Pack, SMD, 13"
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
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74ABT899D,118 datasheet preview Download Datasheet