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Partial File Text FAIRCHILD HIGH SPEED TTL/SSI â¢ 9H08/54H08, 74H08 QUAP 2-INPUT AND GATE LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) [Â¿J [Â¿J UuLJLJLJLJU Positive logic: Y = AB FLATPAK (TOP VIEW) 14 13 12 11 10 SC
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Pb Free Unknown
Lifecycle Unknown

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