DSAE0061700.pdf by QuickLogic

Partial File Text pASIC Macro Library HIGHLIGHTS More than 350 Architecturally Optimized Macros Includes Simple Gates and Advanced Soft Macros Includes Over 100 7400-Series TTL Building Blocks SpDE Packs as Ma
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16 bit adder 16 bit full adder 16 bit ripple adder 2 bit magnitude comparator using 2 xor gates 2-bit half adder 3 bit magnitude comparator 3 bit magnitude comparator using xnor gates 3-input xnor 3-input-XOR 32 bit adder 32 bit ripple carry adder 4 bit binary full adder and subtractor 4 bit binary multiplier 4 bit binary multipliers 4-bit bcd subtractor 4-bit full adder using nand gates 4-bit full adder using nand gates and 3*8 decoder 4-input nand gates ttl 5 bit binary multiplier 7400 datasheet 2-input nand gate 7400 datasheet 4-input nand gate 7400 datasheet nand gate 7400 nand gate 7400 QUAD Nor 7400 TTL 7400 TTL datasheet 7400-series 7400series 8 bit adder and subtractor 8 bit bcd adder subtractor 8 bit binary to 7 segment 8 bit Parallel-Out Shift Register 8 bit XOR Gates BCD adder and subtractor bcd subtractor bcd to hex decoder CI 7400 datasheets of the basic logic gates datasheets of the subtractor using basic logic gate design of 16-1 multiplexer dual tristate xor gate full adder bcd full subtractor decoder using xor and nand gates HALF ADDER half adder using x-OR and NAND gate magnitude comparator using a subtractor quad jk TRIPAD16 ttl 2-bit half adder TTL 7400 TTL 7400 3 input TTL CI 7400 ttl logic gates TTL XOR Gates TTL04 TTL08 TTL145q TTL153 TTL161 TTL163 ttl180 TTL259 TTL279 TTL375 TTL49 TTL684 TTL688 up down counter UPFECT32 XOR en TTL