DSA2IH00158840.pdf by Not Available

Partial File Text 10K / 1 0KH ECL Buffered 10 Tap Delay Modules D2ECL Style Schematic Vcc 10% 3 0 % 5 0% Vcc 60% 8 0 % 1 00 % D32-400 D2ECL .400" Wide DIP 32 Pin Packages, See pg. 31, fig. 4 and Table P-7. GENE
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