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    DSA00102485.pdf by Xilinx

    • P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 D2 D1 S1-B11 S1-C10 S1-A11 S1-B10 TTL1 P1 D4 B1 TTL4 S1-K11 S1-K10 D6 B2 TTL2 TTL5 D5
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