DSAE0065850.pdf by QuickLogic

Partial File Text QAN7 FPGA Cache Controller for the 486DX Russ Lindgren HIGHLIGHTS Zero wait state operation Flexible addressing supports cache RAM sizes from 128K to 1024K Look Aside implementation no mai
Datasheet Type Original
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Pb Free Unknown
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"Lookaside Cache" 486 DX2 component 486 system bus 486DX 486dx schematic 486DX2 cache controller cache ram 64k x 8 cpu schematic gigabyte schematic i486 DX2 PL84C tag 136 TAG 36

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