DSA00104822.pdf by Fairchild Semiconductor

Partial File Text FIN1028 -- 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS)
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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Fairchild DUAL receiver FIN1027 FIN1028 FIN1028M FIN1028MX JESD22-A115 M08AREV13 SOIC127P600X175 SOIC127P600X175-8M

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