DSAZSAA00027536.pdf by Cypress Semiconductor

Partial File Text CY7C1262XV18/CY7C1264XV18 36-Mbit QDRÂ® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDRÂ® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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