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T R I Q U I N T
TOS)
SEMICONDUCTOR,INC.
Figure 1. Block Diagram
VDD
CLKIN
FBIN
SO
PHASE-LOCKED LOOP (PLL)
PHASE CONTROL LOGIC
\ MUX J-
CONFIGURATION LOGIC
GND
0_Q_m m_0_0_a_EL
OUTPUT BUFFER
OUTPUT BUF