DSAZSAA00027908.pdf by Cypress Semiconductor

Partial File Text CY7C1243KV18/CY7C1245KV18 Â® 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDRÂ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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