DSA0095524.pdf by Integrated Device Technology

Partial File Text T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 · Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 · Holdo
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GR-1244-CORE IDT82V3012 SSOP56 TR62411