DSA2IH00181590.pdf by Not Available

Partial File Text 10121B.F LOGIC DIAGRAM B,F PACK AG E CIRCUIT SCHEM ATIC VCC1 ' 1. V c c 2 = 16' V EE = f Positive logic: high level = " l " FEATURES ·Fast propagation delay for 2 logic levels = 2.3 ns T
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