DSAUD0043557.pdf by Cypress Semiconductor

Partial File Text CY7C1329H 2-Mbit (64K x 32) Pipelined Sync SRAM Functional Description[1] Features · Registered inputs and outputs for pipelined operation · 64K × 32 common I/O architecture · 3.3V core powe
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CY7C1329H CY7C1329H-133AXC