DSAUD0051864.pdf
by Silicon Laboratories
- High Speed 8051 µC Core - Pipelined Instruction Architecture; Executes 70% of - Instruction Set in 1 or 2 System Clocks 100 MIPS or 50 MIPS Throughput with On-chip PLL 2-cycle 16 x 16 MAC Engin
- Original
- No
- Unknown
- Not Recommended
- Find it at Findchips.com
