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Partial File Text ï»¿PAIR CHILO SEMICONDUCTOR TM April 1988 Revised March 1999 74F64 4-2-3-2-lnput AND-OR-lnvert Gate General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-I
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74F64 74F64PC 74F64SC 74F64SJ MS-001

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