DSA00123464.pdf by Fairchild Semiconductor

Partial File Text DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inpu
Datasheet Type Original
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Pb Free Unknown
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DM54S112 DM54S112J DM74S112 DM74S112N