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SILICON STACKED GATE MOS INTEGRATED CIRCUIT
TENTATIVE
16M BIT ( 1M W O R D DESCRIPTION
x
16 B 1 T /2 M
WORD x
8 B IT ) CMOS M A S K ROM
T h e T C 5 3 1 6 2 0 0 A F T is a 1 6 ,7 7
