DSA0077284.pdf by Cypress Semiconductor

Partial File Text CY7C1380A CY7C1382A PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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