DSA00360347.pdf by Xilinx

Partial File Text 0 VirtexTM 2.5 V Field Programmable Gate Arrays R 0 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRin
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
Price & Stock
Powered by Findchips

DSA00360347.pdf preview

Download Datasheet

User Tagged Keywords

4096 bit RAM CS144 DS003-2 FPGA Virtex 6 pin configuration TQ144 Virtex xapp151 XCV100 XCV150 XCV200 XCV300 XCV50