DSAUTAZ0016269.pdf by STMicroelectronics
- MUX Figure 1 : Block Diagram 1 - CLOCK GENERATOR DESCRIPTION CKG_CFG[6] (for each (2)) PCMCLK(out) AUXCLK(out) PIXCLK(out) Divider 1 or 2 Divider 1 or 2 Divider 1 or 2 Divider
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