DSASL0075458.pdf by Cypress Semiconductor

Partial File Text CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDRTM-II SRAM 2-Word Burst Architecture Features Configurations Separate Independent Read and Write Data Ports Supports
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CY7C1410JV18 CY7C1412JV18 CY7C1414JV18 CY7C1425JV18 nec 2561