DSAASSA00013903.pdf by Cypress Semiconductor

Partial File Text 36-Mbit QDR II+ Xtreme SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C1263XV18, CY7C1265XV18 ® Featu
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