STACK ORGANISATION
Abstract: l67201 67202
Text: L 67201/L 67202 MATRA MHS 512 x 9 & 1K × 9 / 3.3 Volts CMOS Parallel FIFO Introduction The L67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word
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67201/L
L67201/202
STACK ORGANISATION
l67201
67202
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Untitled
Abstract: No abstract text available
Text: L8C2Q1/2Q2/2Q3/2Q4 L8C201/202/203/204 im 512/1K/2K/4K x 9-bit Asynchronous FIFO DEVICES INCORPORATED FEATURES_ _ □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous
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L8C201/202/203/204
512/1K/2K/4K
IDT720x,
KM75C0x
28-pin
32-pin
L8C201,
L8C202,
L8C203,
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Untitled
Abstract: No abstract text available
Text: L8C201/202/203/204 l o g ic 512/1K/2K/4K x 9-bit Asynchronous FIFO DEVICES INCORPORATED FEATURES_ DESCRIPTION □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous
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L8C201/202/203/204
512/1K/2K/4K
IDT720x,
KM75C0x
L8C202
28-pin
32-pin
L8C201,
L8C202,
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Untitled
Abstract: No abstract text available
Text: Tem ic L 67201/L 67202 MATRA MHS 512 x 9 & 1K x 9 / 3.3 Volts CMOS Parallel FIFO Introduction The L67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.
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67201/L
L67201/202
00QSS7L
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY muMHS DATA SHEET_ _ L March 1994 6 7 2 0 1 /L 6 7 2 0 2 512x9 & 1Kx 9 / 3 . 3 VOLTS CMOS PARALLEL FIFO FEATURES . . . . . . . FIRST-IN FIRST-OUT DUAL PORT MEMORY SINGLE SUPPLY 3.3 ±0.3 VOLTS 512 x 9 ORGANISATION L 67201 1024 x 9 ORGANISATION (L 67202)
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512x9
67201L/202L
7201V/202V
67201/L
67202/R
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Untitled
Abstract: No abstract text available
Text: L O G IC L 8 C 2 0 1 /2 0 2 /2 0 3 /2 0 4 512/1K/2K/4K x 9-bit Asynchronous FIFO mw DEVICES INCORPORATED DESCRIPTION FEATURES □ First-In/First-Out FIFO using Dual-Port Memory □ Advanced CMOS Technology □ High Speed — to 10 ns Access Time □ Asynchronous and Simultaneous
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512/1K/2K/4K
28-pin
32-pin
L8C201
L8C201,
L8C202,
L8C203,
L8C204
L8C204JC25
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Untitled
Abstract: No abstract text available
Text: TO SHIBA TMP47P202V CMOS 4-Bit Microcontroller TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.
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TMP47P202V
TMP47P202VP
TMP47P202VM
47P202V
47C102/202
47P202V
TMM27256AD.
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47C202
Abstract: 47C102
Text: TO SHIBA TMP47P202V CMOS 4-BIT MICROCONTROLLER TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.
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TMP47P202V
TMP47P202VP
TMP47P202VM
47P202V
47C102/202
TMM27256AD.
47C202
47C102
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Untitled
Abstract: No abstract text available
Text: 2bE D LO GI C D E V I CE S INC • 256/512/1K/2K/4K x 9-bit First-In/First-Out FIFO 55bSTOS Q G G l l S b fl ■ _ T - 9 d~3 S ~ L8C200/201 L8C202/203/204 DESCRIPTION FEATURES □ First-In/First Out (FIFO) using Dual-Port Memory Q Highspeed — tol5 ns Access Time
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256/512/1K/2K/4K
55bSTOS
L8C200/201
L8C202/203/204
IDT720x,
KM75C0X
28-pin
32-pin
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47c202
Abstract: BM1187 27256 R4945 tmm27256ad 47C102 DIP20-P-300-2 TMP47P202VM TMP47P202VP
Text: TO SHIBA TMP47P202V CMOS 4-BIT MICROCONTROLLER TMP47P202VP TMP47P202VM The 47P202V is the system evaluation LSI of 47C102/202 with 16K bits one-time PROM. The 47P202V programs/verifies using an adapter socket to connect with PROM programmer, as it is in TMM27256AD.
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P47P202V
TMP47P202VP
TMP47P202VM
47P202V
47C102/202
TMM27256AD.
47c202
BM1187
27256
R4945
tmm27256ad
47C102
DIP20-P-300-2
TMP47P202VM
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Untitled
Abstract: No abstract text available
Text: Environmental Connectors 233-105-00 MIL-DTL-38999 Series III Type Wall Mount Environmental Receptacle Connector Shell Size 09 = A 11 = B 13 = C 15 = D 17 = E 19 = F 21 = G 23 = H 25 = J Basic Part Number 233-105 - D38999 Series III Type Power Connector Finish Material
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MIL-DTL-38999
D38999
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Untitled
Abstract: No abstract text available
Text: Environmental Connectors 233-105-00 MIL-DTL-38999 Series III Type Wall Mount Environmental Receptacle Connector Shell Size 09 = A 11 = B 13 = C 15 = D 17 = E 19 = F 21 = G 23 = H 25 = J Basic Part Number 233-105 - D38999 Series III Type Power Connector Finish Material
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MIL-DTL-38999
D38999
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84L14
Abstract: TR54016 TR62411 XRT84L14IQ XRT84V24 T1-403-1995 GPI06
Text: áç XRT84L14 PRODUCT BRIEF QUAD T1 FRAMER OCTOBER 2000 REV. A1.0.0 GENERAL DESCRIPTION Monitor, Bit Error Rate BER meter, and forced error insertion. The XRT84L14 quad T1/DS1 Framer is a single chip device which integrates 4 T1 framers and transmitters
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XRT84L14
XRT84L14
512-bit
84L14
TR54016
TR62411
XRT84L14IQ
XRT84V24
T1-403-1995
GPI06
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Untitled
Abstract: No abstract text available
Text: CMOS PARALLEL _ FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9 IDT72021 IDT72031 IDT72041 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • ID T 7 202 1/03 1/04 1s are high-speed, low -pow er, du al-port m em ory de vice s com m only know n a s FIFO s F irst-In/FirstO ut . D ata can be w ritte n into and read from the m em ory at
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IDT72021
IDT72031
IDT72041
T72021/
IDT72021,
IDT72031,
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Tcon 8.9 f
Abstract: sharp lcd t-con diagram Sharp TCON RTD2020 lcd ttl tcon TCON 30 pin interface LCD Tcon 18BIT ddc2b rtd20 tcon8
Text: RTD2020 REALTEK FLAT PANEL DISPLAY CONTROLLER RTD2020 Product Brief This document contains introductory information pertaining to the Realtek RTD2020 Flat Panel Display Controller. Because there is proprietary and confidential information contained in the complete specifications, this brief is offered to those interested
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RTD2020
RTD2020
Tcon 8.9 f
sharp lcd t-con
diagram Sharp TCON
lcd ttl tcon
TCON 30 pin interface
LCD Tcon 18BIT
ddc2b
rtd20
tcon8
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Untitled
Abstract: No abstract text available
Text: FAST CMOS 16-BIT REGISTER 3-STATE IDT54/74FCT16374T/AT/CT/ET IDT54/74FCT162374T/AT/CT/ET Integrated Device Technology, In c FEATURES: DESCRIPTION: • Common features: - 0.5 MICRON CMOS Technology - High-speed, low-power CMOS replacement for ABT functions
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16-BIT
IDT54/74FCT16374T/AT/CT/ET
IDT54/74FCT162374T/AT/CT/ET
250ps
MIL-STD-883,
200pF,
FCT16374T/AT/CT/ET:
-32mA
IDT54/74FCT16374T/AT/CT/ET,
162374T/AT/CTÃ
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Untitled
Abstract: No abstract text available
Text: MU9C7201, MU9C7202 MU9C7203, MU9C7204 5 1 2 X 9 , 1K X 9, 2 K X 9 , AND 4K X 9 CMOS FIFOs OCT ATI DISTINCTIVE CHARACTERISTICS High-speed First-in, First-out buffers 50 ns Access, 65 ns Cycle times 15.4 MHz 512 x 9 ,1 K X 9, 2K X 9, and 4K X 9 organizations
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MU9C7201,
MU9C7202
MU9C7203,
MU9C7204
28-pin
32-pin
MU9C7201-MU9C7204
faci-833-3959
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Untitled
Abstract: No abstract text available
Text: S E M I C O N D U C T O R S PRODUCT MU9C0591, MU9C1902, MU9C2903, MU9C4904 0.5K X 9, 1 K X 9 , 2 K X 9 , AND 4K X 9 CMOS FIFOs :OR ATIOI DISTINCTIVE CHARACTERISTICS High-speed First-in, First-out buffers Expandable in depth and width with minimal external logic
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MU9C0591,
MU9C1902,
MU9C2903,
MU9C4904
28-pin
32-pin
o-2156
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PDF
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Untitled
Abstract: No abstract text available
Text: MU9C0591, MU9C1902, MU9C2903, MU9C4904 5 1 2 X 9 , 1 K X 9, 2 K X 9 , AND 4K X 9 CMOS FIFOs D, R ELM N # ö p jic z ,lr E DISTINCTIVE CHARACTERISTICS o High-speed First-in, First-out buffers o 20 ns Access time, 30 ns Cycle time 33 MHz o 512 X 9, 1K X 9, 2K X 9,
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MU9C0591,
MU9C1902,
MU9C2903,
MU9C4904
28-pin
32-pin
U9C2903,
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PDF
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Untitled
Abstract: No abstract text available
Text: 4 TH IS DRAWING 3 IS U N P U B LIS H E D . RELEASED FOR PUBLICATION A L L RIGHTS COPYRIGHT RESERVED. BY TYCO ELECTRONICS CORPORATION. HOUSING COUPLING NUT CLAMP NUT S T A I N L E S S S T E E L PER A S T M - A 4 8 4 AND AST MA582, T Y P E 303 DIELECTRIC
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MA582,
C17300,
MIL-C-14550
RG188/U
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ADN2812
Abstract: ADN2809 ADN2809XCP ADN2809XCP-RL OC48
Text: a Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier Preliminary Technical Data FEATURES Meets SONET Requirements for Jitter Transfer / Generation / Tolerance Quantizer Sensitivity: 6 mV typical • Adjustable Slice Level: +/- 100 mV
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52MHz
44MHz
ADN2809
ADN2812
ADN2809
ADN2809XCP
ADN2809XCP-RL
OC48
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ADN2809
Abstract: ADN2809XCP ADN2809XCP-RL ADN2812 OC48
Text: PRELIMINARY TECHNICAL DATA a Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier Preliminary Technical Data FEATURES Meets SONET Requirements for Jitter Transfer / Generation / Tolerance Quantizer Sensitivity: 6 mV typical • Adjustable Slice Level: +/- 100 mV
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52MHz
44MHz
ADN2809
ADN2809
ADN2809XCP
ADN2809XCP-RL
ADN2812
OC48
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75T203-IP
Abstract: ATB12 75T202-IP
Text: SSI 75T202/203 m 5V Low-Power DTMF Receiver M M b n s A TDK Group/Company October 1991 FEATURES DESCRIPTION The S S I 75T202 and 75T203 are complete Dual-Tone Multifrequency D T M F receivers detecting a se lectable group of 12 or 16 standard digits. No front-end
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75T202/203
75T202
75T203
or75T203
18-pin
75T202-IP
75T203-IP
75T203-IP
ATB12
75T202-IP
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Untitled
Abstract: No abstract text available
Text: For Information Equipment MN5521 I/O Peripheral Controller for PC/AT Computers Overview The MN5521 is an I/O peripheral controller. It is designed for use in combination with the MN5520A CPU controller and the MN871107 floppy disk drive controller in notebook,
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MN5521
MN5521
MN5520A
MN871107
82365SL)
16550-compatible
46818A-compatible
NIOCS16
QFP208-P-2828
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