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    XIP2 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    H16550

    Abstract: xilinx asynchronous fifo baud rate generator vhdl XC2V80 XC2S50E-7
    Text: H16550 - Universal Asynchronous Receiver/Transmitter with FIFOs April 5, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Core documentation EDIF Netlist; VHDL Source RTL Design File Formats available at extra cost


    Original     		PDF H16550 xilinx asynchronous fifo baud rate generator vhdl XC2V80 XC2S50E-7

    1920X1080

    Abstract: MT46V2M32 XIP2069 VHDL code motion 1080p video encoder IP VHDL code integer DCT 6508 RAM vhdl code for sdram controller VHDL code DCT XC2V3000
    Text: MPEG-2 HDTV I & P Encoder April 30, 2002 Product Specification Duma Video, Inc. 11954 NE Glisan Street, #525 Portland, OR 97220 USA Phone: +1 503-550-3040 Fax: +1 503-907-6591 E-mail: info@dumavideo.com URL: www.dumavideo.com Features • • • • • •


    Original     		PDF

    OTU1

    Abstract: XIP2174 Paxonet Communications OC48 ISE4 OTN testbench
    Text: STS48 OTN Framer/Digital Wrapper CC381 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc381.ucf Testbench, test scripts Verification Tool


    Original     		PDF STS48 CC381) cc381 OTU1 XIP2174 Paxonet Communications OC48 ISE4 OTN testbench

    SRL16E

    Abstract: SRL16 XIP2004 XIP2005 XIP2006 XIP2007 XIP2008 SRL16Es binaryencoded Ternary CAM
    Text: Content-Addressable Memory V3.0 March 14, 2002 Product Specification DIN[n:0] WR_ADDR[m:0] DATA_MASK[n:0] Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com


    Original     		PDF XIP2004 SRL16E SRL16 XIP2004 XIP2005 XIP2006 XIP2007 XIP2008 SRL16Es binaryencoded Ternary CAM

    wavelet transform verilog

    Abstract: verilog 2d filter xilinx wavelet transform FPGA 512X512 single port ram testbench vhdl JPEG2000 XIP2015 XIP2016 testbench vhdl ram 16 x 4 testbench verilog ram 16 x 8
    Text: RC_2DDWT: Combine 2D Forward/ Inverse Discrete Wavelet Transform November 30, 2001 Product Specification AllianceCORE Facts Core Specifics See Tables 1 & 2 Provided with Core CAST, Inc. Documentation Design File Formats 11 Stonewall Court Woodcliff Lake, NJ 07677 USA


    Original     		PDF 512x512 JPEG2000 JTC1/SC29/WG11, wavelet transform verilog verilog 2d filter xilinx wavelet transform FPGA single port ram testbench vhdl XIP2015 XIP2016 testbench vhdl ram 16 x 4 testbench verilog ram 16 x 8

    1000BASE-X

    Abstract: vhdl code for defer block coding in mac transmitter verilog code for mdio protocol verilog code for MII phy interface DS200 xip2150 xilinx tcp vhdl
    Text: zozo 1-Gigabit Ethernet MAC Core with PCS/PMA Sublayers 1000BASE-X or GMII v3.0 R DS200 (v1.1) April 30, 2003 Product Specification Features • LogiCORE Facts Single-speed 1-gigabit-per-second Ethernet Media Access Controller (MAC) Core Specifics •


    Original     		PDF 1000BASE-X) DS200 1000BASE-X vhdl code for defer block coding in mac transmitter verilog code for mdio protocol verilog code for MII phy interface DS200 xip2150 xilinx tcp vhdl

    CC-401

    Abstract: XIP209 XIP210 verilog code for spi4.2 interface
    Text: CoreEl SPI-4 Phase 2 Interface Core CC401 May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com


    Original     		PDF CC401) OIF-SPI402 OC-192, CC401 CC410 CC-401 XIP209 XIP210 verilog code for spi4.2 interface

    digital clock program for 89c52

    Abstract: 89c52 controller xcv400hq240 XCV400hq FIR filter matlaB design bandpass 89C52 XIP2191 XIP2192 6 tap FIR Filter XC2S200EPQ208-6
    Text: PDA FIR Filter June 28, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core eInfochips, Inc. Documentation 8 Quail Drive Milpitas, CA 95035 Phone: +1-408-263-2505 Fax: +1-509-461-6192 E-mail: info@einfochips.com URL:


    Original     		PDF 89c52 xcv400hq240-4 xc2s100-6-tq144 xc2v250-5-cs144 xc2s200e-pq208-6 digital clock program for 89c52 89c52 controller xcv400hq240 XCV400hq FIR filter matlaB design bandpass XIP2191 XIP2192 6 tap FIR Filter XC2S200EPQ208-6

    XIP2090

    Abstract: XCV200E-8
    Text: eDCT e-Discrete Cosine Transform April 5, 2002 Product Specification AllianceCORE Facts eInfochips, Inc. 8 Quail Drive Milpitas, CA 95035 Phone: +1-408-263-2505 Fax: +1-509-461-6192 E-mail: info@einfochips.com URL: www.einfochips.com Features • • •


    Original     		PDF

    16 bit register vhdl

    Abstract: XIP2084 XCV200E-8 Xilinx XC2V500
    Text: SHA-1 Processor April 19, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core CAST, Inc. Documentation 11 Stonewall Court Woodcliff Lakes New Jersey 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-Mail: info@cast-inc.com


    Original     		PDF

    data encryption standard vhdl

    Abstract: V400-6 XIP2031 ISE4 V400E-8
    Text: Triple DES Encryption Core January 29, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core CAST, Inc. Documentation Design File Formats 11 Stonewall Court Woodcliff Lakes New Jersey 07677 USA Phone: +1-201-391-8300


    Original     		PDF 168-bit data encryption standard vhdl V400-6 XIP2031 ISE4 V400E-8

    256x16* STATIC RAM

    Abstract: 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50
    Text: Single-Port Block Memory Core v6.2 DS234 April 28, 2005 Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Supports all three Virtex-II write mode options:


    Original     		PDF DS234 256x16* STATIC RAM 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50

    str 5653

    Abstract: STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft
    Text: Fast Fourier Transform v7.0 DS260 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT).


    Original     		PDF DS260 str 5653 STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft

    DS201

    Abstract: 10Gigabit Ethernet PHY vhdl code for ethernet mac spartan 3 VIRTEX-5 DDR PHY xilinx logicore fifo generator 6.2 vhdl code for ethernet csma cd MAC layer sequence number vhdl code for mac transmitter Xilinx ISE Design Suite 9.2i xilinx fifo 9.3
    Text: 10-Gigabit Ethernet MAC v9.3 DS201 September 16, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gbps Ethernet Media Access Controller MAC solution enabling the design


    Original     		PDF 10-Gigabit DS201 10Gigabit Ethernet PHY vhdl code for ethernet mac spartan 3 VIRTEX-5 DDR PHY xilinx logicore fifo generator 6.2 vhdl code for ethernet csma cd MAC layer sequence number vhdl code for mac transmitter Xilinx ISE Design Suite 9.2i xilinx fifo 9.3

    matlab 8 bit booth multiplier

    Abstract: DPRAM 8 bit booth multiplier VERILOG block diagram 8 bit booth multiplier 16 bit multiplier VERILOG booth multiplier mac for fir filter in verilog 4 bit multiplier VERILOG 89c52 controller 89c52 pin diagram
    Text: FIR Filter, DPRAM July 5, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation User Guide, Design Guide EDIF netlist, .ndg, Verilog RTL Design File Formats Constraints File .ucf, .pcf Testbench, test vectors,


    Original     		PDF 89C52 1-509-46lianceCORE matlab 8 bit booth multiplier DPRAM 8 bit booth multiplier VERILOG block diagram 8 bit booth multiplier 16 bit multiplier VERILOG booth multiplier mac for fir filter in verilog 4 bit multiplier VERILOG 89c52 controller 89c52 pin diagram

    PP9094

    Abstract: IDCT design XIP2034 XIP2035
    Text: IDCT: 2D Inverse Discrete Cosine Transform November 30, 2001 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core CAST, Inc. Documentation Design File Formats 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: 201-391-8300


    Original     		PDF 11-bit 12-bit 15-bit PP9094 IDCT design XIP2034 XIP2035

    XIP2173

    Abstract: DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5 CC345
    Text: G.709-Compliant FEC Core CC345 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc345.ucf Testbench, test scripts Verification Tool Instantiation Templates


    Original     		PDF 709-Compliant CC345) cc345 XIP2173 DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5

    RTL code for ethernet

    Abstract: 10-bit-serdes MII PHY verilog code for phy interface 1000BASE-X PRE125 ethernet phy optic 802.3z clause 37 802.3z verilog code for phy interface verilog code of 32 bit mac
    Text: PE-GMAC0 – Gigabit Ethernet FullDuplex Media-Access Controller March 11, 2002 Product Specification AllianceCORE Facts Alcatel Technology Licensing Group 11707 E. Sprague, Suite 306 Spokane, WA 99206 USA Phone: +1 509 777-7604 or (509) 777-7330 Fax:


    Original     		PDF 32-bit/31 25-MHz 32-bit RTL code for ethernet 10-bit-serdes MII PHY verilog code for phy interface 1000BASE-X PRE125 ethernet phy optic 802.3z clause 37 802.3z verilog code for phy interface verilog code of 32 bit mac

    GR-253

    Abstract: XIP211 XIP2198 STS-192 vhdl code for frame synchronization Paxonet Communications
    Text: CoreEl STS192c/STM64 Path Processor CC324 May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com


    Original     		PDF STS192c/STM64 CC324) GR-253, CC324 GR-253 XIP211 XIP2198 STS-192 vhdl code for frame synchronization Paxonet Communications

    XIP2018

    Abstract: XC2V50E-7 XCV200E-8
    Text: AES Encryption Core April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Product Specification, tests set details Design File Formats EDIF Netlist, or VHDL or Verilog Source RTL available at extra cost


    Original     		PDF 1076-Compliant XIP2018 XC2V50E-7 XCV200E-8

    vhdl code for spi

    Abstract: vhdl code for spi xilinx OC192 OC48 XAPP525 verilog code for spi4.2 to fifo spi 4.2 master code verilog code for 16 bit ram SPI Verilog HDL vhdl code for DCM
    Text: Application Note: Virtex-II Series R SPI-4.2 to Quad SPI-3 Bridge XAPP525 v2.0 October 15, 2004 Summary This application note describes a reference design used to bridge one 4-channel Xilinx SPI-4.2 (PL4) core (v6.1) to four 1-channel SPI-3 (PL3) Link Layer cores (v3.2). The design is


    Original     		PDF XAPP525 OC192 com/pub/applications/xapp/xapp525 vhdl code for spi vhdl code for spi xilinx OC48 XAPP525 verilog code for spi4.2 to fifo spi 4.2 master code verilog code for 16 bit ram SPI Verilog HDL vhdl code for DCM

    DS-261

    Abstract: dma controller VERILOG DS261 PCI-X verilog code for pci halfbridge design 4 channels design of dma controller using verilog
    Text: DS261 v1.0 June 23, 2003 PCI-X/PCI HalfBridge Reference Design for Virtex-II Pro, Virtex-II, and Virtex-E FPGAs Product Overview Features • Asynchronous clocks for PCI-X and FPGA operation • • Up to eight DMA Controller(s) Free with purchase of Xilinx PCI-X 64/66 Core


    Original     		PDF DS261 66MHz/64-bit Hz/64-bit DS-261 dma controller VERILOG DS261 PCI-X verilog code for pci halfbridge design 4 channels design of dma controller using verilog

    ise4

    Abstract: example algorithm verilog
    Text: DES Encryption Core January 29, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core CAST, Inc. Documentation 11 Stonewall Court Woodcliff Lakes New Jersey 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-Mail: info@cast-inc.com


    Original     		PDF 56-bit ise4 example algorithm verilog

    OTN testbench

    Abstract: CC481 XIP2196 OTU2 framer OC48 STS192 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder
    Text: STS192 OTN Framer/Digital Wrapper CC481 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc481.ucf Testbench, test scripts Verification Tool


    Original     		PDF STS192 CC481) cc481 OTN testbench XIP2196 OTU2 framer OC48 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder