XILINX SPARTAN XC2S50 Search Results

XILINX SPARTAN XC2S50 Result Highlights (4)

Part	Manufacturer	Description
TPS6508641RSKR	Texas Instruments	Configurable Multi-Rail PMIC for Xilinx MPSoCs and FPGAs 64-VQFN -40 to 85
TPS65086470RSKT	Texas Instruments	Configurable Multi-Rail PMIC for Xilinx MPSoCs and FPGAs 64-VQFN -40 to 85
TPS6508640RSKR	Texas Instruments	Configurable Multi-Rail PMIC for Xilinx MPSoCs and FPGAs 64-VQFN -40 to 85
TPS6508640RSKT	Texas Instruments	Configurable Multi-Rail PMIC for Xilinx MPSoCs and FPGAs 64-VQFN -40 to 85

XILINX SPARTAN XC2S50 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
SPARTAN-II xc2s100 pq208 Abstract: XC2S100 SPARTAN XC2S50 SPARTAN-II xc2s50 pq208 XC2S50 xc2s30 tq144 XC2S150 PQ208 SPARTAN 6 peripherals datasheet XC2S30 board xc2s30 pq208 Contextual Info: Xilinx Confidential and Restricted Page 1 January 6, 2000 Agenda • Spartan Philosophy • Spartan-II FPGAs: Extending Spartan Series • System Integration • Spartan-II family: ASSP Replacement • Summary Xilinx Confidential and Restricted Page 2 January 6, 2000	Original	XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 250Ku CY2000) SPARTAN-II xc2s100 pq208 XC2S100 SPARTAN XC2S50 SPARTAN-II xc2s50 pq208 XC2S50 xc2s30 tq144 XC2S150 PQ208 SPARTAN 6 peripherals datasheet XC2S30 board xc2s30 pq208	PDF
xc17s10xlv08c Abstract: XC17S10XLV08I XC17S20V08C XC17S10XLV08 XC17S20XLV08I XC17S40XLV08I XC17S30XLV08I XC17S05XLV08 XC17S05XLV08C XC17S100L Contextual Info: H XILINX* Spartan Family of PROMs DS030 v1.4 February 18, 2000 Product Specification Introduction Spartan PROM Features The Spartan family of PROMs provide an easy-to-use, cost-effective method for storing Spartan device configura tion bitstreams. •	OCR Scan	DS030 20-pin xc17s10xlv08c XC17S10XLV08I XC17S20V08C XC17S10XLV08 XC17S20XLV08I XC17S40XLV08I XC17S30XLV08I XC17S05XLV08 XC17S05XLV08C XC17S100L	PDF
SPARTAN XC2S50 Abstract: XILINX SPARTAN XC2S50 XCS30XL xc2s50 xcs05xl SPARTAN XCS40XL XC2S30 xc2s30 pq208 xcs10 XC2S150 Contextual Info: Discontinue Low-Volume Members of Spartan, Spartan-XL, and Spartan-II Product Families PDN2004-01 v1.0 March 5, 2004 Product Discontinuation Notice Overview Xilinx is discontinuing selected low-volume device/package combinations of the SpartanTM (5 volt), SpartanXL, and Spartan-II families.	Original	PDN2004-01 CS144, CS280 XCS30 BG256 PQ208 CS144 FG456 SPARTAN XC2S50 XILINX SPARTAN XC2S50 XCS30XL xc2s50 xcs05xl SPARTAN XCS40XL XC2S30 xc2s30 pq208 xcs10 XC2S150	PDF
SPARTAN XCS40XL Abstract: XCS20 XC1701PD8I XC1736EPD8C XC17256EPD8C XC1765EPD8C XC17128EPD8I XC17256E-PD8C XC1765EPD8I XCS10XL Contextual Info: Xilinx FPGAs and PROMs Spartanª, Spartan-XL and Spartan-II FPGAs Continued Spartan/XL Family (Continued) FPGA Package Options and User I/O PLCC IOBs XCS05 77 XCS10 112 XCS20 160 XCS30 192 XCS40 205 XCS05XL 77 XCS10XL 112 XCS20XL 160 XCS30XL 192 XCS40XL	Original	XCS05 XCS10 XCS20 XCS30 XCS40 XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL SPARTAN XCS40XL XC1701PD8I XC1736EPD8C XC17256EPD8C XC1765EPD8C XC17128EPD8I XC17256E-PD8C XC1765EPD8I	PDF
SPARTAN-II xc2s50 pq208 Abstract: SPARTAN-II xc2s100 pq208 SPARTAN XC2S50 XC2S100 XC2S50 SPARTAN Xilinx SPARTAN CS144 FG256 PQ208 Contextual Info: Cover Story THE NEW Spartan-I I FPGA Family KISS YOUR AS IC GOOD-BYE Spartan FPGAs are experiencing tremendous growth due to their inherent advantages over ASICs. Device System Gates Logic Cells Block RAM Bits by Jay Aggarwal, Product Marketing Manager , Spartan Series, Xilinx, jay.aggarwal@xilinx.com	Original	XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S100 SPARTAN-II xc2s50 pq208 SPARTAN-II xc2s100 pq208 SPARTAN XC2S50 XC2S50 SPARTAN Xilinx SPARTAN CS144 FG256 PQ208	PDF
verilog code for fir filter Abstract: FIR FILTER implementation xilinx verilog coding for fir filter digital FIR Filter verilog code digital FIR Filter VHDL code verilog code for discrete linear convolution verilog code for mpeg4 FIR Filter verilog code 8 tap fir filter verilog xilinx FPGA IIR Filter Contextual Info: White Paper: Spartan-II R Xilinx Spartan-II FIR Filter Solution Author: Antolin Agatep WP116 v1.0 April 5, 2000 Introduction Traditionally, digital signal processing (DSP) algorithms are implemented using generalpurpose programmable DSP chips for low-rate applications. Alternatively, special-purpose,	Original	WP116 verilog code for fir filter FIR FILTER implementation xilinx verilog coding for fir filter digital FIR Filter verilog code digital FIR Filter VHDL code verilog code for discrete linear convolution verilog code for mpeg4 FIR Filter verilog code 8 tap fir filter verilog xilinx FPGA IIR Filter	PDF
XC17V00 Abstract: xilinx 8 pin dip Contextual Info: New Products PROMs New High-Density Virtex PROMs and Cost-Effective Spartan-II PROMs Xilinx announces the addition of the XC17V00 and XC17S00A families to its existing line of onetime programmable OTP PROMs. 30 by Theresa Vu Product Marketing Engineer, Xilinx Inc.	Original	XC17V00 XC17S00A xilinx 8 pin dip	PDF
lt1174 Abstract: SPARTAN XC2S50 verilog code ccd lt1174 c AD8036 EL4331 XC2S50 XRD9818 XRD9818ACG XRD9836 Contextual Info: xr XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV. 1.0.0 XRD9818EVAL Evaluation System User Manual 1 xr XRD9818EVAL EVALUATION SYSTEM USER MANUAL REV. 1.0.0 1.0 FEATURES • XRD9818 28-pin TSSOP • FPGA - Xilinx Spartan II XC2S50 • In-System PROM XC18V01	Original	XRD9818EVAL XRD9818 28-pin XC2S50 XC18V01 25-pin EL4331) AD8036) lt1174 SPARTAN XC2S50 verilog code ccd lt1174 c AD8036 EL4331 XC2S50 XRD9818ACG XRD9836	PDF
bga 1296 Abstract: XC2V80 LVDSEXT25 BLVDS-25 LVDSEXT-25 Contextual Info: XILINX FPGA PACKAGE OPTIONS AND USER I/O Pins Body Size I/O’s 88 120 200 264 432 528 624 720 912 1104 1296 176 176 284 316 404 512 660 724 804 804 804 404 556 XC2S200 XC2S150 XC2S100 XC2S50 XC2S30 Spartan-II 2.5V XC2S15 XC2S300E XC2S200E XC2S150E XC2S100E	Original	XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 XC2V250 XC2V500 XCV100E bga 1296 XC2V80 LVDSEXT25 BLVDS-25 LVDSEXT-25	PDF
202 ball bga Abstract: XC2S15 XC2S50E XC2S150 XC2S200 XC2S50 XC2S30 PINS Contextual Info: XILINX SPARTAN FPGAs PRODUCT SELECTION MATRIX DLL Frequency min/max # DLL's Frequency Synthesis Phase Shift Digitally Controlled Impedance Number of Differential I/O Pairs Max. I/O I/O Standards 8 10 12 14 16 32K 40K 48K 56K 64K NA NA NA NA NA 25/320 25/320	Original	XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 202 ball bga XC2S200 XC2S30 PINS	PDF
SPARTAN XC2S50 Abstract: vhdl code for rs232 receiver XAPP213 vhdl code for uart communication UART using VHDL MAX220 SRL16E X223 X233 XAPP223 Contextual Info: Application Note: Virtex Family 200 MHz UART with Internal 16-Byte Buffer R XAPP223 v1.1 July 10, 2001 Author: Ken Chapman Summary This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex , Virtex-E, and Spartan™-II devices. The UART_TX and UART_RX macros not	Original	16-Byte XAPP223 XAPP223 SPARTAN XC2S50 vhdl code for rs232 receiver XAPP213 vhdl code for uart communication UART using VHDL MAX220 SRL16E X223 X233	PDF
XC17S40 Abstract: xilinx SO20 MARKING CODE 17S10L pin diagram of XL 08 UG112 17S10 xc17s30xlpdg8c XC17S30SOG8I TsoP 20 Package XILINX XC17S30 Contextual Info: Product Obsolete or Under Obsolescence X-Ref Target - Figure 0 R Spartan/XL Family One-Time Programmable Configuration PROMs XC17S00/XL DS030 (v1.12) June 20, 2008 Product Specification Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for	Original	XC17S00/XL) DS030 XC17S40 xilinx SO20 MARKING CODE 17S10L pin diagram of XL 08 UG112 17S10 xc17s30xlpdg8c XC17S30SOG8I TsoP 20 Package XILINX XC17S30	PDF
SPARTAN XC2S50 Abstract: SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15 Contextual Info: Robust Feature Set • Flexible on-chip memory Distributed and Block Memory • 4 Digital Delay Lock Loops per device Efficient chip level/ board level clock management • Select I/O Technology Interface to all major bus standards HSTL, GTL, SSTL, etc…	Original	PQ208 FG256 FG456 SPARTAN XC2S50 SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15	PDF
TsoP 20 Package XILINX Abstract: xl marking 17s10l xc17s30xlvo8c XC17S20PD8C SPARTAN XC2S50 xilinx 8 pin dip XCS05 XCS05XL XCS10XL Contextual Info: X-Ref Target - Figure 0 R Spartan/XL Family One-Time Programmable Configuration PROMs XC17S00/XL DS030 (v1.12) June 20, 2008 Product Specification Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for	Original	XC17S00/XL) DS030 20-pin TsoP 20 Package XILINX xl marking 17s10l xc17s30xlvo8c XC17S20PD8C SPARTAN XC2S50 xilinx 8 pin dip XCS05 XCS05XL XCS10XL	PDF

small signal transistor MOTOROLA DATABOOK Abstract: SPARTAN XC2S50 Xilinx SPARTAN XAPP120 XC2S100 XC2S15 XC2S150 XC2S30 XC2S50 CONTRAST ENHANCEMENT VHDL Contextual Info: Application Note: Spartan-XL, Spartan-II R Spartan FPGAs – The Gate Array Solution Author: Ravi Pragasam XAPP120 v2.0 August 1, 2001 Summary This application note discusses the enormous strides made by Spartan series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement.	Original	XAPP120 small signal transistor MOTOROLA DATABOOK SPARTAN XC2S50 Xilinx SPARTAN XAPP120 XC2S100 XC2S15 XC2S150 XC2S30 XC2S50 CONTRAST ENHANCEMENT VHDL	PDF
SPARTAN XC2S50 Abstract: 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 18V00 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A Contextual Info: Xilinx Configuration PROMs XC18V00, XC17V00, XC17S00 FPGA Configuration PROMs 180V00 PROM Family Based on the Xilinx state-of-the-art ISP PROM architecture and manu- • PROM-triggered FPGA reconfiguration via JTAG factured on an advanced 0.35m • Up to 264 MHz configuration speed	Original	XC18V00, XC17V00, XC17S00 180V00 18V00 256Kb 44-pin 20-pin SPARTAN XC2S50 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A	PDF
XC3S200E Abstract: GRM31CR71C106KAC7L XC3S50E XC3S400 GRM188R71C105KA12L GRM188R71H104KA93L XC3S400E XC2S50E Series XC3S700E DC-01-B Contextual Info: 2008 MURATA PRODUCTS POWER SUPPLY REFERENCE GUIDE FOR FPGAs CATALOG No. DC-01-B Please visit our website www.murata.com POWER SUPPLY REFERENCE GUIDE FOR Xilinx® FPGAs Murata offers an extensive selection of DC-DC Converters, both isolated and non-isolated all RoHS compliant .	Original	DC-01-B XC3S200E GRM31CR71C106KAC7L XC3S50E XC3S400 GRM188R71C105KA12L GRM188R71H104KA93L XC3S400E XC2S50E Series XC3S700E DC-01-B	PDF
xilinx 8 pin dip Abstract: XC17S150APD8C XC17S50AVO8C SPARTAN XC2S50 XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S200 Contextual Info: Spartan-II/Spartan-IIE Family OTP Configuration PROMs XC17S00A R DS078 (v1.8) November 18, 2002 5 Advance Product Specification Features • • • • • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for	Original	XC17S00A) DS078 20-pin 44-pin 20-year XC2S400E XC2S600E xilinx 8 pin dip XC17S150APD8C XC17S50AVO8C SPARTAN XC2S50 XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S200	PDF
XILINX SPARTAN XC2S50 Abstract: XCS10XL SPARTAN XC2S50 vq44 XCV100E XCV200E XCV300E XCV50E XC17S Contextual Info: PROMs Reference XC18V FPGA Configurations XC17V XC17S Xilinx offers a full range of configuration memories optimized for use with Xilinx FPGAs. Our PROM product lines are designed to meet the same stringent demands as our high-performance FPGAs and CPLDs, taking full advantage of the	Original	XC18V XC17V XC17S XC1765EL XC17128EL XC17256EL XC17512L XC1701L XC1702L XC1704L XILINX SPARTAN XC2S50 XCS10XL SPARTAN XC2S50 vq44 XCV100E XCV200E XCV300E XCV50E XC17S	PDF
17S100 Abstract: SPARTAN XC2S50 XC17S200APD8 xilinx MARKING CODE xilinx SO20 MARKING CODE 17S150A TsoP 20 Package XILINX XC17S00A XC2S15 XC2S150 Contextual Info: Spartan-II/Spartan-IIE Family OTP Configuration PROMs XC17S00A R DS078 (v1.9) June 24, 2005 5 Product Specification Features • • • • • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices	Original	XC17S00A) DS078 20-pin 44-pin 20-year XC2S400E XC2S600E 17S100 SPARTAN XC2S50 XC17S200APD8 xilinx MARKING CODE xilinx SO20 MARKING CODE 17S150A TsoP 20 Package XILINX XC17S00A XC2S15 XC2S150	PDF
17S40 Abstract: 17S10L XC17S30 17s30 17S40L SPARTAN XC2S50 XC17S30XLVOG8I XC17S40 17s30l XCS05 Contextual Info: Spartan/XL Family One-Time Programmable Configuration PROMs XC17S00/XL R DS030 (v1.11) July 9, 2007 Product Specification 5 Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan , and Spartan-XL FPGAs	Original	XC17S00/XL) DS030 20-pin UG112, XC17S40 XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL, 17S40 17S10L XC17S30 17s30 17S40L SPARTAN XC2S50 XC17S30XLVOG8I 17s30l XCS05	PDF
XC17S200APD8C Abstract: SPARTAN XC2S50 XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S150E XC2S200 XC2S30 Contextual Info: Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs R DS078 v1.5 November 15, 2001 5 Advance Product Specification Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for	Original	DS078 20-pin 44-pin XC17S200APD8C SPARTAN XC2S50 XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S150E XC2S200 XC2S30	PDF
XC17S200APDG8I Abstract: 17S200A SPARTAN XC2S50 XC17S200APDG8 XC17S200APDG8I pin one XC17S200APD8C 17S200 XC17S00A XC2S100 XC2S15 Contextual Info: Spartan-II/Spartan-IIE Family OTP Configuration PROMs XC17S00A R DS078 (v1.10) June 25, 2007 Product Specification 5 Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan -II/Spartan-IIE FPGA devices	Original	XC17S00A) DS078 20-year 20-pin 44-pin XC2S400E XC2S600E XC17S200APDG8I, XC17S200AVOG8I XC17S200APDG8I 17S200A SPARTAN XC2S50 XC17S200APDG8 XC17S200APDG8I pin one XC17S200APD8C 17S200 XC17S00A XC2S100 XC2S15	PDF
17S200 Abstract: 17s50a 17S150A 17s100a 17s200a 17s15a 17s15 17S50 DS078 17S150 Contextual Info: Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs R DS078 v1.6 June 25, 2002 5 Advance Product Specification Features • • • • • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for	Original	DS078 20-pin 44-pin 17S200 17s50a 17S150A 17s100a 17s200a 17s15a 17s15 17S50 DS078 17S150	PDF

XILINX SPARTAN XC2S50 Search Results

XILINX SPARTAN XC2S50 Result Highlights (4)

XILINX SPARTAN XC2S50 Datasheets Context Search

SPARTAN-II xc2s100 pq208

xc17s10xlv08c

SPARTAN XC2S50

SPARTAN XCS40XL

SPARTAN-II xc2s50 pq208

verilog code for fir filter

XC17V00

lt1174

bga 1296

202 ball bga

SPARTAN XC2S50

XC17S40

SPARTAN XC2S50

TsoP 20 Package XILINX

small signal transistor MOTOROLA DATABOOK

SPARTAN XC2S50

XC3S200E

xilinx 8 pin dip

XILINX SPARTAN XC2S50

17S100

17S40

XC17S200APD8C

XC17S200APDG8I

17S200