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    AMD XC6VLX240T-1FF1156C

    IC FPGA 600 I/O 1156FCBGA
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    AMD XC6VLX240T-1FF784C

    IC FPGA 400 I/O 784FCBGA
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    AMD XC6VLX75T-2FFG784I

    IC FPGA 360 I/O 784FCBGA
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    XC6VLX Datasheets (208)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC6VLX130T-1FF1156C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-1FF1156I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-1FF484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-1FF484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-1FF784C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-1FF784I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-1FFG1156C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-1FFG1156I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-1FFG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-1FFG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-1FFG784C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-1FFG784I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-2FF1156C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-2FF1156I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-2FF484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-2FF484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 240 I/O 484FCBGA Original PDF
    XC6VLX130T-2FF784C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-2FF784I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 400 I/O 784FCBGA Original PDF
    XC6VLX130T-2FFG1156C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    XC6VLX130T-2FFG1156I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 600 I/O 1156FCBGA Original PDF
    ...

    XC6VLX Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XC6VLX130T

    Abstract: XC6VLX195T XC5VL110T XC5VL155T PCI33 XC6VLX240T XC5vfx70t XC5VL330T XC4VSX35 ff1156
    Text: XI LI NX VI RTEX -6 FAM I LY FPGAS Virtex-6 LXT FPGAs Virtex-6 SXT FPGAs Optimized for High-Performance Logic and DSP with Low-Power Serial Connectivity 1.0 Volt, 0.9 Volt Part Number EasyPath FPGA Cost Reduction Solutions(1) Logic Resources XC6VLX760T


    Original     		PDF XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760T XC6VSX315T XC6VSX475T XC6VHX250T XC6VLX130T XC6VLX195T XC5VL110T XC5VL155T PCI33 XC6VLX240T XC5vfx70t XC5VL330T XC4VSX35 ff1156

    XC6VLX240T

    Abstract: XAPP882 verilog code of prbs pattern generator verilog code for 64 bit barrel shifter verilog code for 16 bit barrel shifter SFI-5 XC6V 4 bit barrel shifter using mux verilog code for barrel shifter DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER
    Text: Application Note: Virtex-6 Family SERDES Framer Interface Level 5 for Virtex-6 Devices Author: Vasu Devunuri XAPP882 v1.1 May 10, 2010 Summary This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical


    Original     		PDF XAPP882 XC6VLX240T XAPP882 verilog code of prbs pattern generator verilog code for 64 bit barrel shifter verilog code for 16 bit barrel shifter SFI-5 XC6V 4 bit barrel shifter using mux verilog code for barrel shifter DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER

    Untitled

    Abstract: No abstract text available
    Text: XMC Modules XMC-6VLX User-Configurable Virtex-6 FPGA Modules P4 P16 High-Speed SFP Port optional X1 11 LVDS Pairs, 2 Global Clock Pairs, USB, GND X4 X4 36 x 2 JTAG Quad DDR3 SDRAM 2Gb (128M x 16) 36-Pin Connector (optional) XC6VLX240 or XC6VLX365 16 x 4


    Original     		PDF 36-Pin XC6VLX240 XC6VLX365 256Mb 128Mb

    UG365

    Abstract: UG-361 XC6VLX240T UG365 XC6VLX240T-1FFG1156 DSP48E1 VIRTEX-6 UG362 write operation using ram in fpga xc6vlx240t VIRTEX-6 UG373 frequency detection using FPGA
    Text: → 11 Virtex-6 Family Overview DS150 v2.4 January 19, 2012 Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on


    Original     		PDF DS150 DSP48E1 UG369) UG368) XC6VLX760. UG370) UG373) UG365 UG-361 XC6VLX240T UG365 XC6VLX240T-1FFG1156 VIRTEX-6 UG362 write operation using ram in fpga xc6vlx240t VIRTEX-6 UG373 frequency detection using FPGA

    DSP48E1

    Abstract: FPGA Virtex 6 LXT virtex 6 XC6VSX475T XC6VLX240T-1FFG1156 "Binary Multipliers" UG-361 virtex+6 UG366 1000BASE-X DS150
    Text: 11 Virtex-6 Family Overview DS150 v2.1 November 6, 2009 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on


    Original     		PDF DS150 UG364) UG366) XC6VLX760. UG371) XC6VHX250T XC6VHX380T FF1154 DSP48E1 UG369) FPGA Virtex 6 LXT virtex 6 XC6VSX475T XC6VLX240T-1FFG1156 "Binary Multipliers" UG-361 virtex+6 UG366 1000BASE-X DS150

    RAM32M

    Abstract: RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 RAM64M ROM64x1 XC6VLX75T ROM256x1
    Text: Virtex-6 FPGA Configurable Logic Block User Guide Virtex-6 FPGA CLB [optional] UG364 v1.1 September 16, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		PDF UG364 RAM32M RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 RAM64M ROM64x1 XC6VLX75T ROM256x1

    iodelay

    Abstract: XAPP880 OSERDES pmbus verilog FIFO18E1 ML605 ISERDES example ml605 XAPP855 samtec QSE
    Text: Application Note: Virtex-6 FPGAs SFI-4.1 16-Channel SDR Interface with Bus Alignment Using Virtex-6 FPGAs XAPP880 v1.0 February 10, 2010 Author: Vasu Devunuri Summary This application note describes an SFI-4.1 reference design that implements the OIF-SFI4-01.01 interface [Ref 1], a 16-channel, source-synchronous LVDS interface operating


    Original     		PDF 16-Channel XAPP880 OIF-SFI4-01 16-channel, iodelay XAPP880 OSERDES pmbus verilog FIFO18E1 ML605 ISERDES example ml605 XAPP855 samtec QSE

    UG366

    Abstract: XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156
    Text: Virtex-6 FPGA GTX Transceivers User Guide UG366 v2.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG366 UG366 XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156

    UG366

    Abstract: LX760
    Text: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.5 May 17, 2013 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA


    Original     		PDF DS152 UG366 LX760

    CEI11

    Abstract: PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923
    Text: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.0 February 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or


    Original     		PDF UG371 CEI11 PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923

    HW-USB-II-G

    Abstract: NUMONYX xilinx bpi spi flash programmer schematic NUMONYX xilinx spi virtex 5 UG628 XAPP974 fpga radiation spi flash parallel port frame_ecc virtex 6
    Text: Virtex-6 FPGA Configuration User Guide [optional] UG360 v1.0 June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG360 HW-USB-II-G NUMONYX xilinx bpi spi flash programmer schematic NUMONYX xilinx spi virtex 5 UG628 XAPP974 fpga radiation spi flash parallel port frame_ecc virtex 6

    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0

    UG470

    Abstract: local bus to uart using vhdl microblaze XC6VLX240T-1FF UG081
    Text: LogiCORE IP I/O Module v1.00.a DS866 April 24, 2012 Product Specification Introduction LogiCORE Facts The LogiCORE I/O Module is a highly integrated and light-weight implementation of a standard set of peripherals. The I/O Module is a standalone version of the tightly


    Original     		PDF DS866 ZynqTM-7000 UG470 local bus to uart using vhdl microblaze XC6VLX240T-1FF UG081

    fpga frame buffer vhdl examples

    Abstract: axi wrapper matched filter in vhdl RGMII SGMII zynq axi ethernet software example 0x748 verilog code for 10 gb ethernet verilog code for mdio protocol vhdl code for ethernet mac spartan 3
    Text: ‘‘‘‘‘‘‘‘Tri-Mode LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v2.3 DS835 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Virtex -6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the


    Original     		PDF DS835 fpga frame buffer vhdl examples axi wrapper matched filter in vhdl RGMII SGMII zynq axi ethernet software example 0x748 verilog code for 10 gb ethernet verilog code for mdio protocol vhdl code for ethernet mac spartan 3

    XC7K410TFFG676-3

    Abstract: XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000
    Text: LogiCORE IP AXI Timebase Watchdog Timer axi_timebase_wdt (v1.01.a) DS763 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.


    Original     		PDF DS763 32-bit ZynqTM-7000 XC7K410TFFG676-3 XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000

    X485T

    Abstract: AMBA AXI4 verilog code axi wrapper
    Text: Xilinx Design Tools: Release Notes Guide Vivado Design Suite and ISE Design Suite UG631 v2012.2, v14.2 July 25, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum


    Original     		PDF UG631 v2012 X485T AMBA AXI4 verilog code axi wrapper

    SiP12107

    Abstract: SiC403A SiP12108 SiP12109
    Text: VISHAY SILICONIX www.vishay.com Power ICs Application Note FPGA Power Supply Considerations by Owain Bryant ABSTRACT An FPGA is a device that offers many logic elements - up to 1 million gates in a single device at this writing - as well as other functionality such as transceivers, PLLs, and MAC units for complex processing. FPGAs are becoming very powerful, and the


    Original     		PDF SiC401A/B SiC402A/B SiC403A/B SiP12107 05-Mar-13 SiC403A SiP12108 SiP12109

    XC6VLX75T

    Abstract: schematic symbols XTP025 Reed-Solomon encoder
    Text: Reed-Solomon Encoder v7.0 DS251 June 24, 2009 Product Specification Features Applications • Available for all Virtex -4, Virtex-5, Virtex-6, Spartan®-3, Spartan-3A/3AN/3A DSP, Spartan-3E and Spartan-6 FPGAs The Reed-Solomon Encoder is used in many Forward


    Original     		PDF DS251 XC6VLX75T schematic symbols XTP025 Reed-Solomon encoder

    XC6VLX240T-1FFG1156

    Abstract: XC6VLX240T-1FFG DSP48E1 TEMAC XC6VLX240T-1FFG1156C XC6VLX240T UG366 XC6VLX130T UG-361 Virtex 6
    Text: → 11 Virtex-6 Family Overview DS150 v2.2 January 28, 2010 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on


    Original     		PDF DS150 XC6VLX760. UG373) UG363) UG364) XC6VLX240T-1FFG1156 XC6VLX240T-1FFG DSP48E1 TEMAC XC6VLX240T-1FFG1156C XC6VLX240T UG366 XC6VLX130T UG-361 Virtex 6

    axi ethernet lite software example

    Abstract: zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite
    Text: LogiCORE IP Ethernet Lite MAC v1.01a DS787 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AMBA AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3


    Original     		PDF DS787 axi ethernet lite software example zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite

    XC4VLX15-FF668

    Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
    Text: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		PDF DS317 XC4VLX15-FF668 axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan

    d5200c

    Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1
    Text: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit


    Original     		PDF DS777 ZynqTM-7000 d5200c RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1

    AMBA AXI4 verilog code

    Abstract: AMBA AXI specifications AMBA AXI4 pci to pci bridge verilog code Xilinx DS820 system verilog pcie microblaze state machine diagram for axi bridge Xilinx Virtex6 Design Kit 0X138
    Text: LogiCORE IP AXI EP Bridge for PCI Express v1.01.a DS820 October 19, 2011 Product Specification Introduction t LogiCORE IP Facts Table The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express is an interface between the AXI4 bus and PCI Express. Definitions and


    Original     		PDF DS820 64-bit 32-bitthe AMBA AXI4 verilog code AMBA AXI specifications AMBA AXI4 pci to pci bridge verilog code Xilinx DS820 system verilog pcie microblaze state machine diagram for axi bridge Xilinx Virtex6 Design Kit 0X138

    XC6SLX16-CSG324

    Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
    Text: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced


    Original     		PDF DS748 PC16550D PC165otify XC6SLX16-CSG324 XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3