Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    XAPP1 Search Results

    XAPP1 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    XAPP1014

    Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits
    Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1014 XAPP1014 smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits PDF

    XAPP130

    Abstract: verilog code for routing table XCV800 XC4000X XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400
    Text: APPLICATION NOTE  Using the Virtex Block SelectRAM+ XAPP130 October 16, 1998 Version 1.0 13* Advance Application Note Summary The Virtex FPGA Series provides dedicated blocks of on-chip 4096 bit dual-port synchronous RAM. You can use each port of the block SelectRAM+


    Original     		XAPP130 verilog code for routing table XCV800 XC4000X XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 PDF

    dcm_sp

    Abstract: oserdes2 DDR spartan6 UG382 Spartan-6 FPGA DCM_CLKGEN point-to-point mini-lvds oserdes2 XAPP469 OSERDES SP601 Spread-Spectrum
    Text: Application Note: Spartan-6 FPGAs Spread-Spectrum Clock Generation in Spartan-6 FPGAs XAPP1065 v1.0 March 22, 2010 Author: Jim Tatsukawa Summary Consumer display applications commonly use high-speed LVDS interfaces to transfer video data. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)


    Original     		XAPP1065 dcm_sp oserdes2 DDR spartan6 UG382 Spartan-6 FPGA DCM_CLKGEN point-to-point mini-lvds oserdes2 XAPP469 OSERDES SP601 Spread-Spectrum PDF

    XAPP120

    Abstract: XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL rm901
    Text: APPLICATION NOTE  XAPP120 December 2, 1998 Version 1.1 How Spartan Series FPGAs Compete for Gate Array Production Application Note by Ashok Chotai Summary This application note discusses the enormous progress made by FPGAs in the areas of technology, low-price and


    Original     		XAPP120 XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL rm901 PDF

    verilog code 16 bit LFSR

    Abstract: verilog code 8 bit LFSR XAPP131
    Text: 170 MHz FIFOs Using the Virtex Block SelectRAM+  XAPP131 December 10, 1998 Version 1.1 11 Application Note by Nick Camilleri Summary The Virtex FPGA Series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use


    Original     		XAPP131 512x8 170MHz 409other verilog code 16 bit LFSR verilog code 8 bit LFSR PDF

    XAPP151

    Abstract: virtex user guide 1999 XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600
    Text: Virtex Configuration Architecture Advanced Users’ Guide R XAPP151 September 30,1999 Version 1.2 Application Note by Steve Kelem Summary The Virtex architecture supports powerful new configuration modes, including partial reconfiguration. These mechanisms are designed to give


    Original     		XAPP151 32-bit virtex user guide 1999 XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 PDF

    binary to gray code converter

    Abstract: Logic diagram for asynchronous FIFO circuit for binary to gray code converter 4 bit gray to binary converter circuit block diagram for asynchronous FIFO synchronous fifo asynchronous fifo code in verilog vhdl code for asynchronous fifo synchronous fifo design in verilog vhdl code for a grey-code counter
    Text: Application Note: Virtex Series 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature R XAPP131 v1.3 February 2, 2000 Summary The Virtex FPGA Series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note


    Original     		XAPP131 170MHz xapp131h binary to gray code converter Logic diagram for asynchronous FIFO circuit for binary to gray code converter 4 bit gray to binary converter circuit block diagram for asynchronous FIFO synchronous fifo asynchronous fifo code in verilog vhdl code for asynchronous fifo synchronous fifo design in verilog vhdl code for a grey-code counter PDF

    OSERDES

    Abstract: oserdes2 DDR spartan6 XAPP1064 ISERDES2 oserdes2 serdes clock_generator_ddr_s8_diff ISERDES spartan 6 SP601 Clock-Generator
    Text: Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization up to 1050 Mb/s XAPP1064 (v1.0) December 23, 2009 Author: NIck Sawyer Summary Spartan -6 devices contain input SerDes (ISERDES) and output SerDes (OSERDES) blocks. These primitives simplify the design of serializing and deserializing circuits, while allowing


    Original     		XAPP1064 OSERDES oserdes2 DDR spartan6 XAPP1064 ISERDES2 oserdes2 serdes clock_generator_ddr_s8_diff ISERDES spartan 6 SP601 Clock-Generator PDF

    netxtreme 57xx gigabit controller

    Abstract: Broadcom 57xx turbo encoder model simulink 2007A broadcom netxtreme 57xx netxtreme FIR FILTER implementation xilinx ML402 XAPP1031 Co-Simulation
    Text: Application Note: General Use Decreasing Simulation Runtimes with System Generator for DSP Hardware Co-Simulation R Author: Jacobus Naude XAPP1031 v1.0.1 December 19, 2007 Summary This document provides an overview of Hardware Co-Simulation in System Generator for DSP


    Original     		XAPP1031 netxtreme 57xx gigabit controller Broadcom 57xx turbo encoder model simulink 2007A broadcom netxtreme 57xx netxtreme FIR FILTER implementation xilinx ML402 Co-Simulation PDF

    XAPP123

    Abstract: sol 20 Package XILINX XC4000XLA
    Text: Application Note: Spartan-XL, XC4000XLA/XV R Using Three-State Enable Registers in 4000XLA/XV, and Spartan-XL FPGAs XAPP123 v2.0 January 16, 2002 Summary The use of the internal IOB three-state control register can significantly improve output enable and disable time. This application note describes how to use hard macros to implement this


    Original     		XC4000XLA/XV 4000XLA/XV, XAPP123 4000XL) XAPP123 sol 20 Package XILINX XC4000XLA PDF

    XAPP088

    Abstract: XAPP122 XC4000XLA XCS40XL
    Text: Application Note: Spartan-XL R The Express Configuration of Spartan-XL FPGAs XAPP122 v3.0 April 20, 2001 Summary Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. This application note provides information on how to perform Express configuration specifically for


    Original     		XAPP122 XAPP088: com/xapp/xapp088 XAPP088 XAPP122 XC4000XLA XCS40XL PDF

    3014 LED

    Abstract: SPARTAN XC2S50 XAPP176 XAPP188 XC2S100 XC2S100E XC2S15 XC2S150 XC2S200 XC2S30
    Text: Application Note: Spartan-II and Spartan-IIE Families Configuration and Readback of Spartan-II and Spartan-IIE FPGAs Using Boundary Scan R XAPP188 v2.2 June 24, 2005 Summary This application note demonstrates using a Boundary-Scan (JTAG) interface to configure and


    Original     		XAPP188 XAPP176: XAPP176 org/cspress/catalog/st01096 3014 LED SPARTAN XC2S50 XAPP188 XC2S100 XC2S100E XC2S15 XC2S150 XC2S200 XC2S30 PDF

    vhdl code for loop filter of digital PLL

    Abstract: vhdl code for Digital DLL XAPP132 vhdl code for All Digital PLL CLK180 SRL16 XAPP138 vhdl code for phase frequency detector vhdl code for phase shift free vhdl code for pll
    Text: Application Note: Virtex Series R Using the Virtex Delay-Locked Loop XAPP132 v2.8 January 5, 2006 Summary The Virtex FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals


    Original     		XAPP132 vhdl code for loop filter of digital PLL vhdl code for Digital DLL XAPP132 vhdl code for All Digital PLL CLK180 SRL16 XAPP138 vhdl code for phase frequency detector vhdl code for phase shift free vhdl code for pll PDF

    XAPP133

    Abstract: vhdl code for lvds driver d flip-flop PCI33 PQ240 TQ144 BG352 BG432 CS144 HQ240
    Text: Application Note: Virtex Series R Using the Virtex SelectI/O Resource XAPP133 v2.6 November 5, 2002 Summary The Virtex FPGA series includes a highly configurable, high-performance SelectI/O™ resource to provide support for a wide variety of I/O standards. The SelectI/O resource is a


    Original     		XAPP133 XAPP133 vhdl code for lvds driver d flip-flop PCI33 PQ240 TQ144 BG352 BG432 CS144 HQ240 PDF

    Synplify tmr

    Abstract: CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter XAPP216 voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU
    Text: Application Note: Virtex Series R XAPP197 v1.0 November 1, 2001 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only


    Original     		XAPP197 XAPP216, XAPP216 Synplify tmr CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU PDF

    XAPP136

    Abstract: virtex ucf file 6 No Turnaround RAM 1k SRAM Static SRAM XILINX/UCF example for FTP BG432 virtex 5 ddr data path DRAM controller memory FPGA "network interface cards"
    Text: Application Note: Virtex Series and Spartan-II Family Synthesizable 200 MHz ZBT SRAM Interface R XAPP136 v2.0 January 10, 2000 Author: Shekhar Bapat Summary The Virtex series and the Spartan™-II family of FPGAs provide access to a variety of on-chip


    Original     		XAPP136 XAPP136 virtex ucf file 6 No Turnaround RAM 1k SRAM Static SRAM XILINX/UCF example for FTP BG432 virtex 5 ddr data path DRAM controller memory FPGA "network interface cards" PDF

    binary to gray code converter

    Abstract: vhdl code for asynchronous fifo block diagram for asynchronous FIFO asynchronous fifo vhdl 4 bit gray to binary converter circuit 4 bit gray code counter VHDL synchronous fifo 4 bit gray code synchronous counter FIFO error reset full empty synchronous fifo design in verilog
    Text: Application Note: Virtex Series 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature R XAPP131 v1.6 June 5, 2001 Summary The Virtex FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to


    Original     		XAPP131 binary to gray code converter vhdl code for asynchronous fifo block diagram for asynchronous FIFO asynchronous fifo vhdl 4 bit gray to binary converter circuit 4 bit gray code counter VHDL synchronous fifo 4 bit gray code synchronous counter FIFO error reset full empty synchronous fifo design in verilog PDF

    v50bg256

    Abstract: verilog advantages disadvantages XAPP165
    Text: APPLICATION NOTE Using Xilinx and Exemplar for Incremental Designing ECO XAPP165 August 9, 1999 (Version 1.0) Application Note Summary Guided place and route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design


    Original     		XAPP165 v50bg256 verilog advantages disadvantages PDF

    X13002

    Abstract: X13003 XAPP130 x13001 RAM 2816 X130 XC4000X
    Text: Application Note: Virtex Series Using the Virtex Block SelectRAM+ Features R XAPP130 v1.4 December 18, 2000 Summary The Virtex series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can


    Original     		XAPP130 XC4000X 876543210FEDCBA9876543210FEDCBA9876543210 X13002 X13003 XAPP130 x13001 RAM 2816 X130 PDF

    XAPP110

    Abstract: power-sequence XC9500
    Text: APPLICATION NOTE  XC9500 CPLD Power Sequencing XAPP110 February 16, 1998 Version 1.0 3* Introduction Mixed signal systems - typically 5V/3.3V today - require logic parts that can operate with two power supplies. Xilinx XC9500 CPLDs are designed to operate in either mixed


    Original     		XC9500 XAPP110 power-sequence PDF

    vhdl code for spartan 6

    Abstract: The ten commandments digital clock using logic gates XAPP119 XCS30 XCS40 hdl3
    Text: APPLICATION NOTE  XAPP119 July 20, 1998 Version 0.5 Adapting ASIC Designs for Use with Spartan FPGAs Application Note by Kim Goldblatt Summary Spartan FPGAs are an exciting, new alternative for implementing digital designs that, previously, would have


    Original     		XAPP119 vhdl code for spartan 6 The ten commandments digital clock using logic gates XCS30 XCS40 hdl3 PDF

    fundamentals of fdr

    Abstract: BG352 BG432 CS144 HQ240 PCI33 PQ240 TQ144 XAPP133 V2000E
    Text: Application Note: Virtex Series R Using the Virtex SelectI/O Resource XAPP133 v2.5 September 7, 2000 Summary The Virtex FPGA series includes a highly configurable, high-performance SelectI/O™ resource to provide support for a wide variety of I/O standards. The SelectI/O resource is a


    Original     		XAPP133 fundamentals of fdr BG352 BG432 CS144 HQ240 PCI33 PQ240 TQ144 XAPP133 V2000E PDF

    XC9500XL

    Abstract: CS48 PC44 PQ208 TQ100 TQ144 XAPP114
    Text: APPLICATION NOTE Understanding XC9500XL CPLD Power  XAPP114 January 22, 1999 Version 1.1 1* Application Note Summary The goal of this application note is to discuss XC9500XL CPLD power estimation and optimization and provide the reader with an understanding of sense-amplifier based CPLD power dissipation. A brief discussion of the process for estimation is


    Original     		XC9500XL XAPP114 XC9500XL CS48 PC44 PQ208 TQ100 TQ144 PDF

    XAPP137

    Abstract: FPGA Virtex 6 pin configuration XAPP138 CF75h XAPP132 XAPP139 XC4000 XC4000X XC4000XLA XCV50
    Text: Application Note: Virtex Series Virtex FPGA Series Configuration and Readback R XAPP138 v2.5 November 5, 2001 Summary This application note is offered as complementary text to the configuration section of the Virtex data sheet. It is strongly recommended that the Virtex data sheets be reviewed prior to


    Original     		XAPP138 XCV1000 XAPP137 FPGA Virtex 6 pin configuration XAPP138 CF75h XAPP132 XAPP139 XC4000 XC4000X XC4000XLA XCV50 PDF