WISHBONE INTERFACE Search Results

block diagram UART using VHDL

Abstract: wishbone interface for UART LCMXO2-1200HC-4TG144C FSM VHDL interface of rs232 to UART in VHDL LFXP2-5E-5TN144C Lattice LFXP2 NS16450 RD1042 uart verilog testbench
Contextual Info: WISHBONE UART November 2010 Reference Design RD1042 Introduction The Lattice WISHBONE UART provides an interface between the WISHBONE UART system bus and an RS232 serial communication channel. Figure 1 shows the major blocks implemented in the UART in non-FIFO mode. This UART reference design contains a receiver and a transmitter. The receiver performs serial-to-parallel conversion on the asynchronous data

wishbone

Contextual Info: LatticeMico Slave Passthrough The LatticeMico slave passthrough provides a data path between the internal WISHBONE bus and the external WISHBONE slave devices. Version This document describes the 3.2 version of the LatticeMico slave passthrough. Functional Description

ICE40 lattice

Abstract: wishbone
Contextual Info: LatticeMico Master Passthrough The LatticeMico master passthrough provides a data path between the internal WISHBONE bus and the external WISHBONE master devices. Version This document describes the 3.2 version of the LatticeMico master passthrough. Functional Description

vhdl spi interface wishbone

Abstract: verilog code for 8 bit shift register theory VHDL code for slave SPI with FPGA wishbone rev. b LC4256ZE wishbone 4000ZE M68HC11 vhdl code for spi controller implementation on vhdl code for 8 bit shift register
Contextual Info: SPI WISHBONE Controller November 2010 Reference Design RD1044 Introduction The Serial Peripheral Interface SPI bus provides an industry standard interface between microprocessors and other devices as shown in Figure 1. This reference design documents a SPI WISHBONE controller designed to

wishbone

Abstract: Supercool siliconblue memory_passthru
Contextual Info: LatticeMico Memory Passthrough The LatticeMico memory passthrough provides a data path between the internal WISHBONE bus and the external WISHBONE memory devices. Version This document describes the 3.0 version of the LatticeMico memory passthrough. Functional Description

wishbone

Abstract: spi flash controller
Contextual Info: LatticeMico SPI Flash Controller The LatticeMico Serial Peripheral Interface SPI flash controller is a WISHBONE slave device that provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device. The controller has two separate WISHBONE slave ports: Port S and

Sdr sdram controller

Abstract: ICE65 wishbone Supercool 25 1/JESD21-C sdr sdram
Contextual Info: LatticeMico SDR SDRAM Controller The LatticeMico SDR SDRAM controller has a WISHBONE slave port to enable the WISHBONE master in the platform to gain access to the SDRAM memory. Version This document describes the 3.7 version of the LatticeMico SDR SDRAM controller.

addersubtractor

Abstract: adder-subtractor design isplever 2.0 release note, ispvm
Contextual Info: LatticeMico Timer The LatticeMico timer is a highly configurable countdown timer with a WISHBONE-compliant slave interface compatible with the LatticeMico32 microprocessor. Version This document describes the 3.0 version formerly the 7.0 SP2 version of the

Contextual Info: LatticeMico Asynchronous SRAM Controller The LatticeMico asynchronous SRAM controller is a slave device for the WISHBONE architecture. It interfaces to an industry-standard asynchronous SRAM device. Version This document describes the 3.2 version of the LatticeMico asynchronous

ICE40 lattice

Abstract: ispLEVER classic 1.2 memory controller ICE40 FPGA wishbone
Contextual Info: LatticeMico Dual-Port On-Chip Memory Controller The LatticeMico dual-port on-chip memory controller provides two slave interfaces to the WISHBONE bus master ports that allow the ports to access the Lattice Semiconductor FPGA embedded block RAMs EBRs . The

Contextual Info: LatticeMico Parallel Flash Controller The LatticeMico parallel flash memory controller is a slave device for the WISHBONE architecture. It is used to interface with a parallel flash device that is compliant with the common flash memory interface CFI . Version

wishbone

Abstract: LFXP2-5E-5QN208C Lattice LFXP2 wishbone interface LFXP2-5E versatile interface adapter 58NA
Contextual Info: LatticeMico8 to WISHBONE Interface Adapter February 2010 Reference Design RD1043 Introduction The LatticeMico8 8-bit microcontroller is an open IP licensed core that is easily configured for FPGA devices. This versatile microcontroller provides a wide range of capabilities with minimal device resources.

LCMXO2-1200HC-4TG100C

Abstract: LCD module in VHDL LFXP2-5E-5TN144C lcd module verilog "1 wire slave interface" verilog wishbone vhdl for lcd lfxp25e5tn144c Driver/S6A0069 LCMXO2280C-3T100C
Contextual Info: WISHBONE-Compatible LCD Controller November 2010 Reference Design RD1053 Introduction Liquid Crystal Display LCD is a flat display device used in many electronic products. These slim and thin packages, known for their low power characteristics, are an excellent choice for consumer applications. LCD devices

wishbone

Contextual Info: LatticeMico On-Chip Memory Controller The LatticeMico on-chip memory controller provides a slave interface to the WISHBONE bus master ports that allow them access to the Lattice Semiconductor FPGA embedded block RAMs EBRs . The on-chip memory controller automatically instantiates the EBR using the parameterized module

NOR flash controller vhdl code

Abstract: NOR Flash read cycle flash controller verilog code NOR Flash verilog code for Flash controller "NOR Flash" 0x555 wishbone RD1087 verilog code for NOR Flash controller
Contextual Info: NOR Flash Memory Controller with WISHBONE Interface November 2010 Reference Design RD1087 Introduction NOR Flash memory provides random access capabilities to read and write data in specific locations in the memory without having to access the memory in sequential mode. Its high-speed read capacity allows the NOR Flash

ispPAC

Abstract: EFB 45
Contextual Info: LatticeMico EFB The LatticeMico EFB is a hard architectural block that is known as the Embedded Function Block EFB . The EFB includes a Serial Peripheral Interface (SPI), two I2Cs, and a timer/counter peripheral. All of these hard IP peripherals are contained in the EFB block, will connect to the WISHBONE

LatticeMico32

Contextual Info: LatticeMico GPIO The LatticeMico GPIO is a general-purpose input/output core that provides a memory-mapped interface between a WISHBONE slave port and generalpurpose I/O ports. The I/O ports can connect to either on-chip or off-chip logic. Version This document describes the 3.4 version of the LatticeMico GPIO.

verilog code for i2s bus

Abstract: I2S bus specification LCMXO2-1200HC-4TG100 i2s RECEIVER LCMXO2-1200HC-4TG100C wishbone philips I2S bus specification LCMXO1200C-3T100C lcmxo2-1200 verilog i2s
Contextual Info: I2S Controller with WISHBONE Interface November 2010 Reference Design RD1101 Introduction The I2S bus Inter-IC Sound bus is a 3-wire, half-duplex serial link for connecting digital audio devices in an electronic system. The bus handles audio data and clocks separately to minimize jitter that may cause data distortion in

wishbone

Abstract: genesys virtex 5
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

PCI AHB DMA

Abstract: tsmc 0.18 axi bridge
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

ATA hard disk controller

Abstract: HARD DISK diagram RD1095
Contextual Info: IDE/ATA Interface Controller with WISHBONE June 2010 Reference Design RD1095 Introduction Integrated Drive Electronics IDE is one of the most popular data bus interfaces for PCs. The IDE interface links a computer motherboard’s data paths to the computer’s disk storage devices. This interface is known by many different names including ATA, ATA/ATAPI, and EIDE. Although the IDE controller is built into the hard drive, an interface

wishbone rev. b

Abstract: wishbone verilog code for pci to pci bridge verilog hdl code for parity generator RD1008
Contextual Info: PCI/WISHBONE Bridge January 2010 Reference Design RD1045 Introduction PCI Local Bus is an industrial standard developed to seamlessly integrate modern embedded applications into complex systems. Features include a well-documented standard supported by a special interest group and the performance of a 33 MHz, 32-bit version of the specification reaching 132 Mbytes per second at its peak transfer rate.

1000BASE-T2

Abstract: MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format LCMXO640C-4T100C 100Base-T2
Contextual Info: Accessing Control Registers Through the MDIO Bus February 2010 Reference Design RD1074 Introduction Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface SMI to transfer management data between an Ethernet Media