n423
Abstract: n427 ISO 1073-2 iso 2953 N419 n407 n437 n439 n408 n416
Text: ,62, &-7&6&:*N450 Date : 1998-03-23 ,62,(&-7&6&:* ELWDQGELWFRGHVDQGWKHLUH[WHQVLRQ 6(&5(7$5,$7 (/27 DOC TYPE : List of Documents TITLE : ISO/IEC JTC 1/SC 2/WG 3 Document list SOURCE : ISO/IEC JTC 1/SC 2/WG 3 PROJECT: -
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N402R
n423
n427
ISO 1073-2
iso 2953
N419
n407
n437
n439
n408
n416
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Bently nevada CE certification
Abstract: No abstract text available
Text: 3701/55 ADAPT Emergency Shutdown System Bently Nevada* Asset Condition Monitoring Description The 3701/55 Emergency Shutdown Device, ADAPT ESD is a safety PLC with a graphical logic programming interface and integrated overspeed detection. ADAPT ESD is designed for emergency shutdown of rotating machinery such as steam,
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100M8833-01
Bently nevada CE certification
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet Universal Asynchronous Receiver Transmitter UART 2.20 Features • 9-bit address mode with hardware address detection • Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps RX and TX buffers = 4 to 65535
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RS232
RS485.
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Datasheet Universal Asynchronous Receiver Transmitter UART 2.30 Features • 9-bit address mode with hardware address detection • Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps RX and TX buffers = 4 to 65535
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RS232
RS485.
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Synplify tmr
Abstract: CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter XAPP216 voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU
Text: Application Note: Virtex Series R XAPP197 v1.0 November 1, 2001 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only
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XAPP197
XAPP216,
XAPP216
Synplify tmr
CC16CE
vhdl code hamming edac memory
vhdl code for a grey-code counter
voter
CC16RE
vhdl coding for error correction and detection algorithms
vhdl code hamming
RAM EDAC SEU
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Synplify tmr
Abstract: voter vhdl code for a grey-code counter CC16CE MUXCY CC16SE SRL16 XAPP197 XAPP216 vhdl coding for hamming code
Text: Application Note: Virtex Series R XAPP197 v1.0.1 July 6, 2006 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only
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XAPP197
XAPP216,
XAPP216
Synplify tmr
voter
vhdl code for a grey-code counter
CC16CE
MUXCY
CC16SE
SRL16
XAPP197
vhdl coding for hamming code
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8250A
Abstract: INS8250 intel 8250 block diagram of microcontroller voting machine ssm 8511 B10M INS8250A M82510 MCS-51 LSR220
Text: M82510 ASYNCHRONOUS SERIAL CONTROLLER Military Y Y Y Asynchronous Operation 5- to 9-Bit Character Format Baud Rate DC to 288k Complete Error Detection Y MCS -51 9-Bit Protocol Support Y Control Character Recognition Y CHMOS III with Power Down Mode Multiple Sampling Windows
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M82510
28-Lead
28-Pad
16-bit
8250A
INS8250
intel 8250
block diagram of microcontroller voting machine
ssm 8511
B10M
INS8250A
M82510
MCS-51
LSR220
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voting machine code
Abstract: No abstract text available
Text: Software Development Tools Cygnus Support Cygnus Developer's Kit -CDK Standard Features Why Cygnus Support? ❏ ANSI conformant GNU C compiler or GNU C+ compiler currently tracking ANSI standard A software development team is only as productive as the tools that support them. Cygnus Support has taken
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Untitled
Abstract: No abstract text available
Text: PSoC Creator Component Data Sheet Universal Asynchronous Receiver Transmitter UART 2.0 Features • 9-bit address mode with hardware address detection • BAUD rates from 110 – 921600 bps or arbitrary up to 3 Mbps • RX and TX buffers = 1 – 65535
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RS-232
RS-485.
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lin uart c code
Abstract: No abstract text available
Text: PSoC Creator Component Data Sheet Universal Asynchronous Receiver Transmitter UART 1.50 Features • 9-bit address mode with hardware address detection • BAUD rates from 110 – 921600 bps or arbitrary up to 3 Mbps • RX and TX buffers = 1 – 65535
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RS-232
RS-485.
lin uart c code
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VOTING MACHINE COUNTER
Abstract: uarts
Text: PSoC Creator Component Datasheet Universal Asynchronous Receiver Transmitter UART 2.10 Features • 9-bit address mode with hardware address detection • Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps RX and TX buffers = 4 to 65535
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RS232
RS485.
VOTING MACHINE COUNTER
uarts
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dtx 360 transistor
Abstract: ALP 101 modulator MAS9191A TQFP64 15HEX 8001FF transistor dtx 360
Text: DA9191A.000 July 31, 1997 MAS9191A Single Chip AMPS/ETACS/NAMPS Audio/Data Processor • • • • Single chip solution for all audio and data processing Low power consumption with several power down modes SAT decoding and transponding circuitry Simple 4-wire serial interface
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DA9191A
MAS9191A
MAS9191A
dtx 360 transistor
ALP 101 modulator
TQFP64
15HEX
8001FF
transistor dtx 360
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MOB4 nxp
Abstract: MOB6 nxp MOB6 MOB4 package P304G003A4 mifare 4k MOB6 nxp P308G003 MOB4 p308g003a4
Text: NXP Smart eID : fixed functionality secure IC solution Smart eID optimized for single-application contactless smart cards Designed for basic identity documents, these standards-based, fixed-function ICs are supported by full integrated application software. They support compact memory sizes, simplify development,
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ALP 101 modulator
Abstract: 300Hz-3kHz dtx 360 transistor MAS9191A 100mVDC 2.2nf capacitor transistor dtx 360
Text: DA9191A.000 July 31, 1997 0$6 $ 6LQJOH &KLS $036 7$&61$036 $XGLR'DWD 3URFHVVRU • • • • 6LQJOH FKLS VROXWLRQ IRU DOO DXGLR DQG GDWD SURFHVVLQJ /RZ SRZHU FRQVXPSWLRQ ZLWK VHYHUDO SRZHU GRZQ PRGHV 6$7 GHFRGLQJ DQG WUDQVSRQGLQJ FLUFXLWU\ 6LPSOH ZLUH VHULDO LQWHUIDFH
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DA9191A
MAS9191A
ALP 101 modulator
300Hz-3kHz
dtx 360 transistor
100mVDC
2.2nf capacitor
transistor dtx 360
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MAX9217
Abstract: MAX9218 MAX9218ECM MAX9218ETM rgbout video in RGBout
Text: 19-3557; Rev 5; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control
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27-Bit,
3MHz-to-35MHz
MAX9218
MAX9217
MAX9218
MAX9218ECM
MAX9218ETM
rgbout
video in RGBout
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MAX9217
Abstract: MAX9218 MAX9218ECM MAX9218ETM
Text: 19-3557; Rev 4; 5/08 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control
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27-Bit,
3MHz-to-35MHz
MAX9218
MAX9217
MAX9218ECM
MAX9218ETM
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RTAXSGenDesc_DS
Abstract: microcontroller voting machine hamming code block diagram of microcontroller voting machine voting machine ZILOG Z180 real time application of D flip-flop hamming test bench circuit cellar voting machine code
Text: FEATURE ARTICLE by Monte D a lry m p le Designing for Hostile Environments Monte recently designed a CPU that will one day orbit Jupiter in one of the most hostile envi ronments in the solar system. In this article, he describes design techniques that you can use
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Y180-S:
yl80s
RTAXSGenDesc_DS
microcontroller voting machine
hamming code
block diagram of microcontroller voting machine
voting machine
ZILOG Z180
real time application of D flip-flop
hamming test bench
circuit cellar
voting machine code
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M62510
Abstract: LEM Hais 100-P
Text: in te i* M82510 ASYNCHRONOUS SERIAL CONTROLLER Military m Asynchronous Operation • MCS -51 9-Bit Protocol Support — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection ■ Control Character Recognition ■ CHMOS III with Power Down Mode
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M82510
16-blt
28-Lead
28-Pad
M62510
LEM Hais 100-P
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Untitled
Abstract: No abstract text available
Text: M82510 ASYNCHRONOUS SERIAL CONTROLLER Military • MCS -51 9-Bit Protocol Support ■ ■ Control Character Recognition ■ Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection ■ CHMOS III with Power Down Mode
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M82510
16-blt
28-Lead
28-Pad
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290116
Abstract: intel 29011
Text: intei 82510 ASYNCHRONOUS SERIAL CONTROLLER MCS-51 9-Bit Protocol Support • Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection IBM PC AT* INS 8250A /16450 Software Compatible Control Character Recognition
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MCS-51
28-Lead
16-Bit
290116
intel 29011
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block diagram of microcontroller voting machine
Abstract: 82510 8250A 82510 loopback ICM280 2D706 INS8250 INS8250A MCS-51 290116
Text: www.Datasheet. i n in te l 82510 ASYNCHRONOUS SERIAL CONTROLLER Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection Multiple Sampling Windows Two, Independent, Four-Byte Transmit and Receive FIFOs with Programmable
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16-Bit
MCS-51
250A/16450Â
28-Lead
block diagram of microcontroller voting machine
82510
8250A
82510 loopback
ICM280
2D706
INS8250
INS8250A
290116
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intel 82310
Abstract: 82310 intel 8250A SERIAL 8250 spf mir 003 02 intel 29011 Remote Control Toy TRANSMITTER IC
Text: 82510 ASYNCHRONOUS SERIAL CONTROLLER Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection MCS-51 9-Bit Protocol Support IBM PC AT* INS 8250A/16450 Software Compatible Control Character Recognition
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16-Bit
MCS-51
250A/16450)
28-Lead
intel 82310
82310 intel
8250A
SERIAL 8250
spf mir 003 02
intel 29011
Remote Control Toy TRANSMITTER IC
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Untitled
Abstract: No abstract text available
Text: in te i 82510 ASYNCHRONOUS SERIAL CONTROLLER Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection MCS-51 9-Bit Protocol Support IBM PC AT* INS 8250A/16450 Software Compatible Control Character Recognition
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MCS-51
250A/16450Â
16-Bit
28-Lead
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82510
Abstract: 8250A girl INS8250 INS8250A MCS-51 1474h 290116
Text: 82510 ASYNCHRONOUS SERIAL CONTROLLER • Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection MCS-51 9-Bit Protocol Support IBM PC AT* INS 8250A/16450 Software Compatible Control Character Recognition
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16-Bit
MCS-51
250A/16450Â
28-Lead
82510
8250A
girl
INS8250
INS8250A
1474h
290116
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