Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    VHDL CORDIC CODE Search Results

    VHDL CORDIC CODE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DM7842J/883 Rochester Electronics LLC DM7842J/883 - BCD/Decimal Visit Rochester Electronics LLC Buy
    9310FM Rochester Electronics LLC 9310 - BCD Decade Counter (Mil Temp) Visit Rochester Electronics LLC Buy
    54LS48J/B Rochester Electronics LLC 54LS48 - BCD-to-Seven-Segment Decoders Visit Rochester Electronics LLC Buy
    TLC32044IFK Rochester Electronics LLC PCM Codec, 1-Func, CMOS, CQCC28, CC-28 Visit Rochester Electronics LLC Buy
    TLC32044IN Rochester Electronics LLC PCM Codec, 1-Func, CMOS, PDIP28, PLASTIC, DIP-28 Visit Rochester Electronics LLC Buy

    VHDL CORDIC CODE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    vhdl code for cordic algorithm

    Abstract: vhdl code for cordic verilog code for cordic algorithm vhdl code for modulation vhdl code for complex multiplication and addition verilog code for cordic vhdl code for rotation cordic vhdl code for digital clock digital clock vhdl code cordic algorithm code in verilog
    Text: New Products - Software Programming a Xilinx FPGA in “C” Hardware designers are realizing they will need to use higher levels of abstraction to increase their productivity. by Doug Johnson, Business Development Manager, Frontier Design, doug_johnson@frontierd.com; Marc Defossez, Field Applications Engineer,


    Original     		PDF

    source code verilog for qr decomposition

    Abstract: verilog code for 4 bit multiplier testbench matlab code for mimo ofdm verilog code for mimo ofdm vhdl code for cordic algorithm RLS matlab verilog code for inverse matrix cordic vhdl code for rotation cordic CORDIC vhdl altera
    Text: QR Matrix Decomposition Application Note 506 February 2008, ver. 2.0 Introduction QR matrix decomposition QRD , sometimes referred to as orthogonal matrix triangularization, is the decomposition of a matrix (A) into an orthogonal matrix (Q) and an upper triangular matrix (R). QRD is useful


    Original     		PDF

    VERILOG Digitally Controlled Oscillator

    Abstract: matlab code to generate sine wave using CORDIC verilog code of sine rom verilog code to generate sine wave QFSK EP3C10F256 verilog code for digital modulation cyclone iii matlab code for half adder CORDIC to generate sine wave fpga VHDL code for CORDIC to generate sine wave
    Text: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 11.0 May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    verilog code for CORDIC to generate sine wave

    Abstract: verilog code for cordic algorithm vhdl code for cordic vhdl code for rotation cordic CORDIC to generate sine wave fpga verilog code to generate sine wave vhdl code to generate sine wave verilog code for cordic CORDIC to generate sine wave vhdl code for FFT 32 point
    Text: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    verilog code for cordic algorithm

    Abstract: CORDIC to generate sine wave fpga vhdl code for cordic cosine and sine sin wave with test bench file in vhdl vhdl code for cordic algorithm cordic algorithm code in verilog CORDIC altera matlab code to generate sine wave using CORDIC vhdl code for rotation cordic QFSK
    Text: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 9.1 November 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    fsk by simulink matlab

    Abstract: VHDL code for CORDIC to generate sine wave VERILOG Digitally Controlled Oscillator vhdl code for cordic algorithm verilog code for cordic algorithm vhdl code to generate sine wave matlab code to generate sine wave using CORDIC verilog code for CORDIC to generate sine wave vhdl code for cordic matlab code for CORDIC to generate sine wave
    Text: NCO Compiler MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: 2.0.1 Document Version: 2.0.1 rev. 1 Document Date: July 2002 Copyright NCO Compiler MegaCore Function User Guide Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,


    Original     		PDF

    verilog code to generate sine wave

    Abstract: verilog code for sine wave generator using cordic vhdl code to generate sine wave CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave vhdl code dds VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm vhdl code for cordic CORDIC to generate sine wave
    Text: CoreDDS Handbook Actel Corporation, Mountain View, CA 94043 2006 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200078-0 Release: September 2006 No part of this document may be copied or reproduced in any form or by any means


    Original     		PDF

    wireless power transfer matlab simulink

    Abstract: wcdma simulink vhdl code for cordic Crest factor reduction CORDIC vhdl altera verilog code for histogram simulink model verilog code for cdma simulation FIR filter matlaB design code FIR filter matlaB design altera
    Text: Crest Factor Reduction Application Note 396 June 2007, Version 1.0 This application note describes crest factor reduction and an Altera crest factor reduction solution. Overview A high peak-to-mean power ratio causes the following effects: • ■ In-band distortion:


    Original     		PDF

    vhdl code for cordic algorithm

    Abstract: verilog code for cordic verilog code for logarithm verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic verilog code for cordic algorithm sine cosine vhdl code for cordic cosine and sine vhdl cordic code verilog code of sine rom
    Text: DCORDIC CORDIC processor ver 1.16 OVERVIEW The DCORDIC uses the CORDIC algorithm to compute trigonometric, reverse trigonometric, hyperbolic and reverse hyperbolic functions. It supports sine, cosine, arcus tangent functions for hyperbolic and trigonometric systems. Logarithm, square root and exponent


    Original     		PDF 24-bit IEEE-754 vhdl code for cordic algorithm verilog code for cordic verilog code for logarithm verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic verilog code for cordic algorithm sine cosine vhdl code for cordic cosine and sine vhdl cordic code verilog code of sine rom

    8051 16bit addition, subtraction

    Abstract: verilog code for floating point division verilog code for single precision floating point multiplication vhdl code for cordic cosine and sine vhdl code for cordic verilog code for floating point multiplication program for 8051 16bit square root vhdl code for cordic multiplication test bench for 16 bit shifter verilog code for cordic
    Text: Floating Point Mathematics Unit ver 1.30 OVERVIEW DFPMU uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign of a number


    Original     		PDF IEEE-754 16-bit 32-bit 32-bit 8051 16bit addition, subtraction verilog code for floating point division verilog code for single precision floating point multiplication vhdl code for cordic cosine and sine vhdl code for cordic verilog code for floating point multiplication program for 8051 16bit square root vhdl code for cordic multiplication test bench for 16 bit shifter verilog code for cordic

    verilog code for floating point multiplication

    Abstract: vhdl code for cordic cosine and sine vhdl code for 8 bit floating point processor verilog code for single precision floating point multiplication verilog code for cordic verilog code for double precision floating point multiplication 8051 16bit addition, subtraction verilog code for single precision floating point addition DP8051 IEEE 754
    Text: DFPMU-DP Floating Point Coprocessor Double Precision ver 3.03 OVERVIEW DFPMU-DP is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU-DP directly replaces C software functions, by equivalent, very fast hardware


    Original     		PDF

    verilog code for floating point multiplication

    Abstract: vhdl code for cordic cosine and sine vhdl code for cordic VHDL code for floating point addition verilog code for floating point division vhdl code for cordic multiplication program for 8051 16bit square root verilog code for single precision floating point multiplication 8051 16bit addition, subtraction CORDIC sine cosine float altera
    Text: DFPMU Floating Point Coprocessor ver 2.05 OVERVIEW DFPMU is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU directly replaces C software functions, by equivalent, very fast hardware operations,


    Original     		PDF DP8051, 32-bit verilog code for floating point multiplication vhdl code for cordic cosine and sine vhdl code for cordic VHDL code for floating point addition verilog code for floating point division vhdl code for cordic multiplication program for 8051 16bit square root verilog code for single precision floating point multiplication 8051 16bit addition, subtraction CORDIC sine cosine float altera

    vhdl code for cordic cosine and sine

    Abstract: verilog code to generate sine wave vhdl code to generate sine wave verilog code for CORDIC to generate sine wave CORDIC to generate sine wave qpsk modulation VHDL CODE verilog code for cordic algorithm sine cosine VHDL code for CORDIC to generate sine wave vhdl code for cordic algorithm matlab code to generate sine wave using CORDIC
    Text: NCO Compiler MegaCore Function Solution Brief 49 September 2000, ver. 1.0 Target Applications: Data Storage and Retrieval Systems, Modulators, Demodulators, and Digital PLLs Features • ■ Family: APEXTM 20K, ACEXTM, FLEX 10, FLEX 8000, and FLEX 6000 ■


    Original     		PDF

    vhdl code for rotation cordic

    Abstract: DS858 LogiCORE IP CORDIC CORDIC divider CORDIC in xilinx cordic design for fixed angle rotation CORDIC v5.0 CORDIC v4.0 XC7K325T CORDIC system generator xilinx
    Text: LogiCORE IP CORDIC v5.0 DS858 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP v5.0 core implements a generalized coordinate rotational digital computer CORDIC algorithm. Features Core Specifics Supported


    Original     		PDF DS858 ZynqTM-7000, vhdl code for rotation cordic LogiCORE IP CORDIC CORDIC divider CORDIC in xilinx cordic design for fixed angle rotation CORDIC v5.0 CORDIC v4.0 XC7K325T CORDIC system generator xilinx

    cordic sine cosine generator vhdl

    Abstract: cordic vhdl code for cordic algorithm vhdl code for cordic vhdl code for rotation cordic vhdl code for vector cordic verilog code for cordic verilog code for cordic algorithm cordic algorithm code in verilog vhdl code for cordic cosine and sine
    Text: CoreCORDIC CORDIC RTL Generator Product Summary • – Intended Use • COordinate Rotation DIgital Computer CORDIC Rotator Function for Actel FPGAs Vector Rotation – Conversion of Polar Coordinates to Rectangular Coordinates • Vector Translation – Conversion of Rectangular


    Original     		PDF

    MIMO OFDM Matlab code

    Abstract: matlab code for mimo ofdm vhdl code for cordic qr decomposition vhdl code for digital to analog converter papr in ofdm using matlab OFDM Matlab code MATLAB code for decimation filter VHDL for decimation filter serial analog to digital converter vhdl code vhdl code for serial analog to digital converter
    Text: Digital radio series Altera wireless solutions Simplify your RF card design cycle By integrating Altera programmable logic devices PLDs into the core of your radio frequency (RF) cards, you gain flexibility and high performance, plus a risk-free migration path to low-cost structured


    Original     		PDF R251332 SS-01004-2 MIMO OFDM Matlab code matlab code for mimo ofdm vhdl code for cordic qr decomposition vhdl code for digital to analog converter papr in ofdm using matlab OFDM Matlab code MATLAB code for decimation filter VHDL for decimation filter serial analog to digital converter vhdl code vhdl code for serial analog to digital converter

    matlab code for FFT 32 point

    Abstract: vhdl code for 16 point radix 2 FFT using cordic a wimax matlab vhdl code for 16 point radix 2 FFT OFDM Matlab code fft matlab code using 8 point DIT butterfly Crest factor reduction vhdl code for cordic algorithm OFDMA Matlab code matlab code using 16 point radix2
    Text: Crest Factor Reduction for OFDMA Systems Application Note 475 November 2007, ver. 1.0 Introduction Crest factor reduction CFR is a technique for reducing the peak-toaverage ratio (PAR) of an orthogonal frequency division multiplexing (OFDM) waveform. An OFDM signal is made up in the frequency


    Original     		PDF

    lms algorithm using verilog code

    Abstract: lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer verilog code for lms adaptive equalizer for audio digital IIR Filter VHDL code 8086 microprocessor based project verilog DTMF decoder qpsk demodulation VHDL CODE verilog code for fir filter using DA
    Text: AMPP Catalog June 1998 About this Catalog June 1998 AMPP Catalog Contents This catalog provides information on Altera Megafunction Partners Program AMPPSM partners and provides descriptions of megafunctions from each AMPP partner. The information in this catalog is current as of


    Original     		PDF

    full subtractor implementation using NOR gate

    Abstract: fpga based 16 QAM Transmitter for wimax application with quartus fpga based 16 QAM Transmitter for wimax application with matlab 256POINT vhdl code for rotation cordic WCDMA DUC CORDIC altera cordic sine cosine generator vhdl vhdl code for radix 2-2 parallel FFT for ofdm vhdl code for radix-4 fft
    Text: DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_ADV-1.0 Document Version: Document Date: 1.0 June 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    matlab programs for impulse noise removal

    Abstract: verilog code for cordic algorithm for wireless verilog code for CORDIC to generate sine wave block interleaver in modelsim matlab programs for impulse noise removal in image vhdl code for cordic matlab programs for impulse noise removal in imag vhdl code to generate sine wave PLDS DVD V9 CORDIC to generate sine wave fpga
    Text: DSP Builder Handbook Volume 1: Introduction to DSP Builder 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_INTRO-1.0 Document Version: Document Date: 1.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    verilog code for distributed arithmetic

    Abstract: verilog code for fir filter using DA vhdl code for FFT based on distributed arithmetic 8 bit Array multiplier code in VERILOG verilog code for fir filter using MAC digital FIR Filter verilog code vhdl code for dFT 32 point vhdl code for FFT 32 point CORDIC system generator xilinx verilog code for correlator
    Text: Xilinx DSP High Performance Signal Processing January 1998 New High Performance DSP Alternative New advantages in FPGA technology and tools: Xilinx DSP offers a new alternative to ASICs, fixed function DSP devices, and DSP processors. This DSP solution is achieved through the introduction


    Original     		PDF

    GSM 900 simulink matlab

    Abstract: verilog code for ofdm transmitter fir filter coding for gui in matlab digital IIR Filter VHDL code digital IIR Filter verilog code qpsk modulation VHDL CODE vhdl code for ofdm transmitter vhdl code for ofdm turbo codes qam system matlab code qpsk demapper VHDL CODE
    Text: Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a Programmable-Chip Designs May 2001 Signal Processing IP: Proven Performance in One Portfolio performance, high-throughput signal coding schemes, W processing algorithms. ireless and digital signal processing DSP


    Original     		PDF M-GB-SIGNAL-01 GSM 900 simulink matlab verilog code for ofdm transmitter fir filter coding for gui in matlab digital IIR Filter VHDL code digital IIR Filter verilog code qpsk modulation VHDL CODE vhdl code for ofdm transmitter vhdl code for ofdm turbo codes qam system matlab code qpsk demapper VHDL CODE

    Marvell PHY 88E1111 Datasheet

    Abstract: 88E1145 88E1111 PHY registers map 88E1111 marvell ethernet switch sgmii verilog code for cordic algorithm using 8-fft SMPTE425M verilog code for CORDIC to generate sine wave scaler verilog code dc bfm
    Text: MegaCore IP Library Release Notes and Errata 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Library Version: 8.1 Document Version: 8.1.3 Document Date: 1 February 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    verilog code for 32-bit alu with test bench

    Abstract: verilog code for single precision floating point multiplication 8051 16bit division 80C51 DR80390 DR80390CPU DR80390XP DR8051 DR8051CPU 80C390
    Text: DR80390XP High Performance Configurable 8-bit Microcontroller ver 3.10 OVERVIEW DR80390XP is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast typically on-chip and slow (off-chip) memories. The core has been designed with a


    Original     		PDF DR80390XP DR80390XP 80C390 DR80390XP: verilog code for 32-bit alu with test bench verilog code for single precision floating point multiplication 8051 16bit division 80C51 DR80390 DR80390CPU DR8051 DR8051CPU 80C390