VBB VCC VEE Search Results

AN1003

Abstract: 100LVEL32 100EL32
Contextual Info: SK10/100EL32W ¸2 Divider HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL32W is an integrated ¸2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to VCC with

SK100EL32WDT

Contextual Info: SK10/100EL32W ÷2 Divider HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL32W is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to VCC with

100LVEL32

Contextual Info: SK10/100EL32W ¸2 Divider HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL32W is an integrated ¸2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to VCC with

Contextual Info: MC10125L IL00 ECL ECL-TO-TTL TRANSLATOR —TOP VIEW— 16 GND VBB 1 15 14 13 12 11 10 2 3 4 5 6 7 9 VCC VEE 8

2SA1015

Abstract: 2SC1815 2SC1815 2SA1015 2SA1015 G 2SC1815 G 2sa1015 equivalent 1SS181 1SS184 1SS226 1SS272
Contextual Info: 応用回路例 [8] 3. スイッチング回路 インバータ回路 1 3.1 VCC NPN トランジスタの場合 VCC PNP トランジスタの場合 RL RL CK CK 出力 入力 RG RK 出力 Q1 入力 RB RG Q1 RK RB VBB VBB 回 トランジスタ Q1 2SA1015

100LVEL16

Contextual Info: SK10/100EL16XWA-XWG High Gain Differential Receiver HIGH-PERFORMANCE PRODUCTS Description the output swing can be obtained by a variable resistor between the VBB and VCC pins, with wiper driving CTRL. Typical application circuits and results are described in Figures 3, 4a, and 4b.If provided,

100LVEL16

Abstract: SK10EL16XWGMS
Contextual Info: SK10/100EL16XWA-XWG High Gain Differential Receiver PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description the output swing can be obtained by a variable resistor between the VBB and VCC pins, with wiper driving CTRL. Typical application circuits and results are described in Figures 3, 4a, and 4b.If provided,

Contextual Info: New Data CD54/74HC4316 CD54/74HCT4316 1916 File N um b er High-Speed CMOS Logic vcc '61 Quad Analog Switch with Level Translation Type Features: LOGIC LEVEL CONV. ANO teONTROÜ f i • W ide a n a lo g -in p u t-v o lta g e ran ge Vcc-Vbb : 0 -1 0 V ■ Low "ON" re s is ta n c e : 45 Q ty p . @ Vcc=4.5 V

T0060

Abstract: CDCM7005 DIVBY16
Contextual Info: CDCM7005 www.ti.com SCAS793 – JUNE 2005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER GND GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND GND GND GND VCXO or VCC E VCXO_IN GND

Contextual Info: SK100LVE111 1:9 Differential LVECL/LVPECL Clock Driver TEST AND MEASUREMENT PRODUCTS Description the LVE111 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to VCC via a 0.01 µF capacitor. The SK100LVE111 is a low skew 1-to-9 differential driver

U321

Abstract: AD6645SQ AD8138ARM DATA SHEET D434 74LCX574 AD6644 AD6645 AD8138ARM MC100LVEL16 NC7SZ32
Contextual Info: 6 5 4 3 2 1 +3P3VD DO NOT INSTALL +5VA DC COUPLED ENCODE OPTION SEE NOTE 3 C6 0.01U 5 +V 1 BUFLAT +5VA +5VA 2 1 D 7 D Q D C5 0.01U Q 4 R13 66.5 R11 66.5 VCC +3P3VD U7 6 3 VEE VBB 1 (SEE NOTE 4) 5 16 2 2 15 3 3 14 4 4 13 5 5 12 6 6 11 7 CR1 7 10 8 2 8 R12

16D14

Contextual Info: LOW-POWER HEX ECL-to-TTL TRANSLATOR SY100S325 FINAL DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset

F100K

Abstract: SY100S325 SY100S325FC SY100S325JC SY100S325JCTR
Contextual Info: LOW-POWER HEX ECL-to-TTL TRANSLATOR SY100S325 DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset

F100K

Abstract: SY100S325 SY100S325FC SY100S325FCTR SY100S325JC
Contextual Info: LOW-POWER HEX ECL-to-TTL TRANSLATOR Micrel, Inc. DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 3.7ns IEE min. of –37mA TTL outputs Extended supply voltage option: VEE = –4.2V to –5.5V 25% faster than National's 325

F100K

Abstract: SY100S314 SY100S314FC SY100S314JC SY100S314JCTR
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER FEATURES SY100S314 FINAL DESCRIPTION • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

F100K

Abstract: SY100S314 SY100S314FC SY100S314JC SY100S314JCTR
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER FEATURES SY100S314 DESCRIPTION • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

100EL90

Abstract: Application Note AND8002/D
Contextual Info: MC100EL90 −3.3V / −5V Triple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL

F100K

Abstract: SY100S314 SY100S314FC SY100S314JC SY100S314JCTR
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER FEATURES SY100S314 DESCRIPTION • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

100lvel90

Contextual Info: MC100LVEL90 −3.3V / −5V Triple ECL Input to LVPECL Output Translator The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to +3.3 V differential LVPECL

100EL17

Contextual Info: MC100EL17 5V ECL Quad Differential Receiver The MC100EL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output

F100K

Abstract: SY100S314 SY100S314FC SY100S314FCTR SY100S314JC
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER Micrel, Inc. SY100S314 SY100S314 DESCRIPTION FEATURES • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

F100K

Abstract: SY100S314 SY100S314JC SY100S314JCTR
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER Micrel, Inc. SY100S314 SY100S314 DESCRIPTION FEATURES • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

SY100E116

Abstract: SY10E116 SY10E116JC
Contextual Info: QUINT DIFFERENTIAL LINE RECEIVER FEATURES SY10E116 SY100E116 DESCRIPTION • 450ps max. Propagation Delay ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E116 are quint differential line receivers designed for use in new, high-performance ECL systems.

100lvel90

Abstract: MC100LVEL90 MC100LVEL90DW MC100LVEL90DWR2
Contextual Info: MC100LVEL90 −3.3V / −5V Triple ECL Input to LVPECL Output Translator The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to +3.3 V differential LVPECL