U4J SWITCH Search Results

murs460

Abstract: MURS460C
Contextual Info: MURS460C SURFACE MOUNT SUPER FAST RECTIFIERS REVERSE VOLTAGE – 600 Volts FORWARD CURRENT – 4.0 Amperes FEATURES • Glass passivated chip SMC • Super fast switching for high efficiency • For surface mounted applications • Low forward voltage drop and high current capability

74hc14m

Abstract: M74HC14M1R IC 74LS14 hex inverter with schmitt trigger DATA IC 74LS14 M74HC14
Contextual Info: M54HC14 M74HC14 SCS-THOMSON M HEX SCHMITT INVERTER HIGH SPEED tpD = 11 ns TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 1 nA (MAX.) AT Ta = 25 ”C HIGH NOISE IMMUNITY VH = 1.1 V (TYP.) AT Vcc = 5 V OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS SYMMETRICAL OUTPUT IMPEDANCE

Contextual Info: Formosa MS Chip Ultra Fast Rectifiers MURS460 List List. 1 Package outline. 2 Features. 2

1000MF

Abstract: AN2150S AN2250S
Contextual Info: AN2250S AN2250S CCD \ZT3Ì" f i * 7 fflfl|-?- iälH lK /CCD Video Camera S ign al P rocessin g Circuit I tfS ^ AN2250S i, C C D t'f-^ ^ ^ ««<m , ? m ft L ± -t„ m • f f i S f i , f i « ii! t iij ii: v cc = 5.0v, Icc = 17mA(typ. • 7 x - K, is v m n f t f r m & P lM

Contextual Info: Preliminary Commercial IN C . PEEL 22CV1 OAZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 133 product term x 44 input AND array — Up to 22 inputs and 10 I/O pins — 12 possible macrocell configurations

PEEL20CG10AJ-15

Contextual Info: Commercial/ Industrial INC.- PEEL 20CG10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Up to 12 configurations per macrocell

Contextual Info: Commercial/ Industrial INC. PEEL 22CV10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features High Speed/Low Power — Speeds ranging from 5ns to 25ns — Power as low as 67mA at 25MHz Architectural Flexibility — 132 product term X 44 input AND array

Contextual Info: ¡ET Preliminary Commercial INC. PEEL 20V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features Compatible with Popular 20V8 Devices — 20V8 socket and function compatible — Programs with standard 20V8 JEDEC file — 24-pin DIP/SOIC, 28-pin PLCC packages

Contextual Info: PEEL 16V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features Low Power and Quarter Power Versions — Low Power: 75mA typical Ice — Quarter Power: 45mA typical Icc • Compatible with Popular 16V8 Devices — 16V8 socket and function compatible

OZ815LN

Abstract: ITE8512 BG41 ah44 ALC662 OZ8602 oz815 CH7318 JMB360 USBP11N
Contextual Info: Chapter2 Page 1 of 39 Major Components Chapter2 Major Components 2.1. System Block Diagram ………………………………………………… 3 2.2. Major Component Definition .…….……………………………….… 28 2.3. Connector Definition…….………………………………………………

HP 2602

Abstract: HCPL-66XX a 2631 optocoupler optocoupler NAND dual flip flop 8-pin HP 2601 optocoupler HP 2602 optocoupler 6N137 HCPL-0600 HCPL-2612
Contextual Info: What H E W L E T T WL'IIM P A C K A R D High CMR Line Receiver Optocouplers Technical Data HCPL-2602 HCPL-2612 F eatures A pplications D escrip tion • 1000 V/|_ls Minimum Common Mode R ejection CMR at Vcm = 50 V fo r HCPL-2602 and 3.5 kV/JJs Minimum CMR a t VCM = 300 V for

OZ815LN

Abstract: oz815 OZ8602 nb9p ALC662 it85 OZ860 ITE8512 SAMA5 AJ47
Contextual Info: Chapter2 Page 1 of 49 Major Components Chapter2 Major Components 2.1. System Block Diagram ………………………………………………… 3 2.2. Major Component Definition .…….……………………………….… 38 2.3. Connector Definition…….………………………………………………

29DL400TC

Contextual Info: FLASH MEMORY 4M 512K x 8/256K x 16 BIT CMOS M B M 2 9 D L 4 0 0 T C -55-70-90-12/M B M 29 D L400B C-5 5 -70 -90-12 • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Simultaneous operations Read-while-Erase or Read-while-Program

asus

Abstract: 47n217 R7790 C5706 c5701 R5314 ISL6262CRZ ICS954310BGLFT rtl8111b powerload
Contextual Info: A B C D E A8J/F SCHEMATIC 1 Content PAGE PAGE SYSTEM PAGE REF. 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 YONAH CPU 1 YONAH CPU (2) CPU CAP/THERMAL SENSOR CLOCK GEN. Calistoga-CPU

QG82945PM

Abstract: asus R7790 47n217 isl6227caz ISL6262CRZ rtl8111b d5702 C5022 R5538
Contextual Info: A B C D E A8Jp/Jv/Je/Jn/Fm SCHEMATIC 1 Content PAGE PAGE SYSTEM PAGE REF. 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Merom CPU 1 Merom CPU (2) CPU CAP/THERMAL SENSOR CLOCK GEN.

V3V REV-1.1

Abstract: asus C5027 r d5703 X7RA 47N217 C5706 c6005 3VA2 ICS954310BG
Contextual Info: A B C D E A8J/F SCHEMATIC R11 1 Content PAGE PAGE SYSTEM PAGE REF. 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 YONAH CPU 1 YONAH CPU (2) CPU CAP/THERMAL SENSOR CLOCK GEN. Calistoga-CPU

O2Micro ozh24tn

Abstract: LA-4841P KB926 ICS9LPRS397 SN0806081 OZH24 SN0806081RHBR 2C156 ich9 isl6268caz-t
Contextual Info: A B C D E 1 1 Compal Confidential 2 2 Schematic Document Cantiga + ICH9 2008 / 12 / 10 Rev:1.0 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 2008/1/15 Deciphered Date Title Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

YT 24628

Abstract: 2709759 LT517 270975 intel 80c188 8086 interrupt structure 8086 microprocessor block diagrammed with direction 24619 AA 80C188 instruction set interrupt 8086 nmi
Contextual Info: in te i 80C188XL20, 16, 12, 10 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR L o w P o w e r, Fult S ta tic V ersio n o f th e 80C 188 D ire c t A d d res sin g C a p a b ility to 1 M b yte M e m o ry and 64 K b yte I/O O p e ra tio n M o d e s Include: — E n hanced M o d e

p1503bvg

Abstract: OZ8602 OZ815LN P0603BVG oz815 CH7318 tr 2n3904 C1284 P0603B ITE8512
Contextual Info: 5 D 4 3 2 1 Project Name : F50IXX Platform : Montevina Penryn CPU +Cantiga(NB)+ICH9M(SB)+NB9P/M D Schematic Version Change History PAGE CONTENT 1. INDEX 39. NB9P/M LVDS / TMDS 2. SYSTEM BLOCK DIAGRAM 40. NB9P/M SS / BIOS / HDCP 3. POWER DIAGRAM & SEQUENCE

KB926

Abstract: LA-4231P LA-4131P FBMA-L11-201209-221LMA30T LA-4121 LA-4231P REV 1A OZ129 JAL80 si7686 LA4231
Contextual Info: A B C D E 1 1 Compal Confidential 2 2 Schematic Document Crestline + ICH8 2007 / 11 / 14 Rev:0.2 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 2008/1/15 Deciphered Date Title Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

BT-183

Abstract: POWER SUPPLY BOARD T583 asustek bt183 asus T5027 C5706 TP2804 Z62fm z62fp r1601 C7370
Contextual Info: 5 4 3 2 1 Z62FM Block Diagram CPU VCORE FAN + SENSOR CPU YONAH-2M PAGE 50 D Power On Sequence PAGE 4 PAGE 39 D SYSTEM PWR PAGE 2,3 PAGE 51 CLOCK GEN ICS954310 FSB 667MHz BAT & CHARGER PAGE 5 PAGE 57 MCH-M Calistoga 945GM LVDS & INV PAGE 12 PortBAR3 CRT CRT & TV OUT

88SA804

Abstract: marvell 88SA8040 LA-2721 88sa8040 Socket AM2 Compal Electronics 23/88sa8040 ic CV 203 HP 4515 915GM
Contextual Info: A B C D E 1 1 Boston LA-2721 Schematics Document 2 2 Intel Dothan / Alviso GM PM / DDR-1 / ICH6-M (nVIDIA NV44MV / ATi M24C) Rev:1.0 3 3 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2005/05/06 Issued Date Deciphered Date 2006/05/06

bcm4401kql

Abstract: foxconn marvell 88SA8040 la-2151 88SA8040 DELL power supply diagram h240as-00 compal LPC47N354 sst39vf080-70-4c-ei max1987
Contextual Info: A B C D E COMPAL CONFIDENTIAL 1 MODEL NAME : TOBAGO COMPAL P/N : 45128331001/45128331002 PCB NO : LA2151 Revision : 0.4 DELL: X03 1 TOBAGO Schematics Document 2 2 uFCBGA/uFCPGA Mobile Dothan Intel Alviso + ICH6M 2004-06-15 REV : 0.4 (DELL: X03) 3 3 4 4 DELL CONFIDENTIAL/PROPRIETARY

kbc 1098

Abstract: KBC1098-NU smsc kbc 1091 kbc1098 Smsc kbc1098 MMBT3904WH 2N7002DWH smsc kbc 1098 HCB2012KF-121T50 RTM890N-632-GRT
Contextual Info: A B C D E 1 1 Compal Confidential Schematics Document 2 2 INTEL AUBURNDALE with IBEX core logic Cartier UMA 3 3 LA-4902P 2009-12-07 REV:1.0 4 4 Compal Secret Data Security Classification 2008/09/15 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL