U2002D Search Results

485G

Abstract: NB7L14M NB7L14MMNG NB7L14MMNR2G
Contextual Info: NB7L14M 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for

KVT23

Abstract: MC100LVELT23 2x2 dfn
Contextual Info: MC100LVELT23 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead

AC600V

Abstract: AEQ10410 AEQ10417 AEQ10418 AEQ11510 AEQ11517 AEQ11518 RH96
Contextual Info: 微小負荷用スイッチ （100 A 3V DC 対応） EQスイッチ RoHS対応 特 長 ●微小負荷対応100μA 3V DC〜100mA 30V DC ●J型同等サイズで超ロングストローク。O.T. （ピン押 ボタン型） でNO側2.2mm以上/NC側2.5mm以上

Contextual Info: STB Self-Checking Optical Touch Buttons † Self-Checking Ergonomic Actuating Devices Features • Diverse-redundant microcontroller-based photoelectric touch buttons • Continuous internal self-checking operation • Ergonomically designed to eliminate hand, wrist and arm stresses associated with

EPT25

Abstract: KPT25 MC100EPT25
Contextual Info: MC100EPT25 -3.3V / -5V Differential ECL to +3.3V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small outline 8−lead package and the single gate of the EPT25 make it ideal

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: NB7L14M 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for

marking 2U diode

Abstract: marking 2U 20 diode KLT25 marking code 8 lead soic package marking codes 2u Diode 2U 26 diode marking 2u marking 84 ELT25 HLT25
Contextual Info: MC10ELT25, MC100ELT25 -5 V Differential ECL to TTL Translator Description Features • • • MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 2.6 ns Typical Propagation Delay 100 MHz FMAX CLK 24 mA TTL Outputs Flow Through Pinouts Operating Range: VCC = 4.5 V to 5.5 V with GND = 0 V;

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

Contextual Info: NB100ELT23L 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

Contextual Info: NB7L14M 2.5V/3.3V Differential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for

KPT21

Abstract: MC100EPT21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

AND8020

Abstract: ELT23L KT23L NB100ELT23L
Contextual Info: NB100ELT23L 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

KVT23

Abstract: MC100LVELT23 2x2 dfn
Contextual Info: MC100LVELT23 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead

KPT21

Abstract: MC100EPT21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

HLT21

Abstract: 74 TTL series k 3555 marking 84 MC10ELT21DG ELT21 KLT21 MC100 MC100ELT21 MC10ELT21
Contextual Info: MC10ELT21, MC100ELT21 5 V Differential PECL to TTL Translator Description • • • • • • 3.5 ns Typical Propagation Delay 24 mA TTL Output Flow Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V Q Output Will Default LOW with Inputs Left Open or < 1.3 V

EPT23

Abstract: KPT23 MC100EPT23 2x2 dfn
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21 2x2 dfn
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KR22

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

KVT22

Abstract: KR22 MC100LVELT22 948R
Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

KPT23

Abstract: EPT23 MC100EPT23
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: MC100LVELT23 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead

EPT22

Abstract: KPT22 MC100EPT22
Contextual Info: MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8−lead

Contextual Info: MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8−lead