TWO WAY SET ASSOCIATIVE CACHE Search Results

MPC509

Abstract: tag126
Contextual Info: SECTION 4 INSTRUCTION CACHE The MPC509 instruction cache I-cache is a 4-Kbyte, two-way set associative cache. The cache is organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on four-word boundaries in memory.

MPC860

Contextual Info: SECTION 10 DATA CACHE 10.1 OVERVIEW The MPC860 data cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. Two state bits are included in each cache line and

MPC821

Abstract: TAG126
Contextual Info: SECTION 10 DATA CACHE 10.1 OVERVIEW The MPC821 data cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. Two state bits are included in each cache line and

powerpc 403gcx

Abstract: 403GCX PPC403GCX tis14
Contextual Info: PowerPC 403GCX 32-Bit RISC Data Sheet Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative

403gcx

Abstract: 403GCX-3JC66C2 powerpc 403gcx 403GCX-3JC50C2 PPC403GCX 403GCX-3JC80C2 D2271 IBM powerpc tis14
Contextual Info: PowerPC 403GCX 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative

403GCX

Abstract: powerpc 403gcx 403GCX-3JC66C2 403GCX-3JC50C2 403GCX-3JC80C2 403GCX-3BC66C2 403GCX-3BC80C2 PPC403GCX
Contextual Info: PowerPC 403GCX 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative

TAG 9101

Abstract: R/TRIAC tag 9101 MPC860 stream register cache coherency (1/TAG 9101
Contextual Info: SECTION 9 INSTRUCTION CACHE 9.1 OVERVIEW The MPC860 instruction cache I-cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction

R/TRIAC tag 9101

Abstract: MPC821 TAG 9101
Contextual Info: SECTION 9 INSTRUCTION CACHE 9.1 OVERVIEW The MPC821 instruction cache I-cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction

TAG62

Abstract: MPC823
Contextual Info: SECTION 9 INSTRUCTION CACHE The MPC823 instruction cache is a 2K two-way, set associative storage area. It is organized into 64 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock

intel xmm 6140

Abstract: DQ45CB 43LA xmm 6140 81348 61RA 100C AA10 PAR64 PC3200
Contextual Info: Intel 81348 I/O Processor Datasheet Product Features Two Integrated Intel XScale processors — 667 MHz, 800 MHz and 1.2 GHz — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way Set Associative, NRU Replacement Algorithm, Lockable — Unified Level 2 Cache: 512 KByte Set

81348

Abstract: 3150* intel
Contextual Info: Intel 81348 I/O Processor Datasheet Product Features Two Integrated Intel XScale processors — 667 MHz, 800 MHz and 1.2 GHz — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way Set Associative, NRU Replacement Algorithm, Lockable — Unified Level 2 Cache: 512 KByte Set

MEA 2901

Abstract: I486dx 82490dx 241084 21A27 Intel 82495 Cache Controller L486 AT 30B 82495DX i486 bus interface
Contextual Info: in te i Intel486 DX CPU-CACHE CHIP SET 50 MHz Intel486™ DX Microprocessor, 82495DX Cache Controller, and 82490DX Dual Ported Intelligent Cache SRAM High Performance Second Level Cache — Two-Way Set Associative — Write-Back or Write Through Cache Zero Wait State Cache Access

MPC823

Contextual Info: SECTION 10 DATA CACHE The MPC823 data cache is a 1K two-way, set-associative cache. It is organized into 32 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical data

80960JT

Abstract: 80960VH AD10 MA11
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

80960JT

Abstract: 80960VH AD10 MA11 273179
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

A10 bga

Abstract: intel flash memory W18 80960JT 80960VH AD10 MA11
Contextual Info: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

80960VH

Abstract: INTEL DX2 80960JT AD10 MA11 cc5r
Contextual Info: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

485Turbocache

Abstract: 82485M
Contextual Info: intei 485TURBOCACHE MODULE Intel486 MICROPROCESSOR CACHE UPGRADE 82485MA 64k Module 82485MB (128k Module) High Performance — Zero Waitstate Access — One Clock Bursting — Two-Way Set Associative — BIOS ROM Cacheing — 25/33 MHz Operation Range Of Price/Performance

241814

Abstract: pentium 1993 PentiumTM multiprocessing
Contextual Info: intei 82496 CACHE CONTROLLER AND 82491 CACHE SRAM FOR USE WITH THE PentiumTM PROCESSOR High Performance Second Level Cache — Zero Wait States at 66 MHz — Two-way Set Associative — Write-Back with MESI Protocol — Concurrent CPU Bus and Memory Bus Operation

Contextual Info: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 High Performance 80960JF Core — Sustained One Instruction/Clock Execution — 4 Kbyte Two-Way Set-Associative

82485

Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers

CACHE

Contextual Info: SECTION 5 INSTRUCTION CACHE The instruction cache I-cache is a 4-Kbyte, 2-way set associative cache. The cache is organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory. A cache access cycle begins with an instruction request from the CPU instruction

TA114

Abstract: BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486
Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel