TTL MEMORY Search Results

Z8000

Abstract: Z8001 Z8002 lm 8002 amz8000 Z8001 package HA 1166 Z8000 package size
Contextual Info: i Am8127 < AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Four TTL-level clocks G enerates synchronized TTL com patible clocks at 16MHz, 2M Hz and 1MHz to drive memory circuits and LSI peripheral devices. An additional TTL clock is synchronized with the CPU high-level clock for

led clock circuit diagram

Abstract: ECL IC NAND ic 3842 datasheet DAC ic 0808 pin diagram 3842 smps IC 8 pin ic 3842 MCK12140 application note ADC 10 Ghz 266 XnOR GATE NB3N551
Contextual Info: Complete Clock Management Solutions Processor Skew Tuning 1 HCSL TTL-to-PECL Translator Multiplexer LVDS TTL/CMOS LVDS/HCSL Loop Filter VCO 10 ZDB ASIC Memory 1 CMOS/TTL Divider/ Prescaler PE/EQ Processor 9 1 Discrete PLL Blocks Processor 5 1 PECL/CML Phase

LM 8002

Abstract: amz8000 Z8001 crystal OSCILATOR 4mhz Z8000 Z8002 AmZ8
Contextual Info: i Am8127 < AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Four TTL-level clocks G enerates synchronized TTL com patible clocks at 16MHz, 2M Hz and 1MHz to drive memory circuits and LSI peripheral devices. An additional TTL clock is synchronized with the CPU high-level clock for

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

DTL or TTL integrated logic circuits

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450APC

Abstract: 9109 DC fairchild ECL 75450a
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75452ATC

Abstract: 75452A
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

754538

Abstract: 9109 DC 55450B 75450BDC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

74 TTL PACKAGE OUTLINES

Abstract: 75451ATC 1606B 55451A 75451ARC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450apc

Abstract: 10125 ecl to ttl fairchild 9112 7S45 pin diagram for all 74 series ttl gates
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75451

Abstract: 55450B 75452B fairchild 9112
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75452

Abstract: 55450B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

fairchild ECL

Abstract: 75453btc 55450B 754S3B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

Contextual Info: PRELIMINARY CMOS EEPROM KM93C56V/KM93C66V 2 K /4 K Bit Serial Electrically Erasable PROM FEATURES GENERAL DESCRIPTION • Enhanced extended operating voltage: 3.0V~5.5V • Low power consumption — Active: 3 mA TTL — Standby: 250fiA (TTL) • Memory organization:

signetics 723

Abstract: cewe cl 48
Contextual Info: 54F189A Signetics 64-Bit TTL Bipolar RAM, Inverting 3-State Objective Specification Military Logic Products FEATURES APPLICATIONS DESCRIPTION • Address access time: 9ns Max • Scratch pad memory • Power dissipation: 4.3mW/bit typ • Buffer memory • Schottky clamped TTL

TMS4116

Abstract: TMS4116-15 TMS4116-20 TMS4116-25
Contextual Info: TMS4116 16,384-BIT DYNAMIC RANDOM ACCESS MEMORY OCTOBER 1977 —REVISED NOVEMBER 1986 • 1 6 ,3 8 4 X 1 Organization • 10% Tolerance on All Supplies • All Inputs Including Clocks TTL Compatible • Unlatched Three-State Fully TTL-Compatible Output •

Contextual Info: National Semiconductor DM77/87SR193 2k x 8 16k-Bit Registered TTL PROM General Description The DM77/87SR193 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chip. This device is organized as 2k words by 8

D3493

Abstract: SN100KT5538 Texas Instruments TTL
Contextual Info: SN100KT5538 OCTAL ECL-TO-TTL TRANSLATOR WITH OPEN-COLLECTOR OUTPUTS _ D 3493. A P R IL 1990 DW OR NT PACKAGE 100K Compatible TOP VIEW Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers ECL and TTL Control Inputs * * * Y1[

Hex schmitt trigger ecl

Abstract: Dual Retriggerable Resettable One Shots ECL 100315 cmos function generator DIP 4 Crystals Clock Generators MM74C14 DIP CRYSTAL MM74C221 monostable ttl
Contextual Info: Logic Products by Function Other Products Logic Product Family Product Description Package Voltage Node 9403A FAST First-In First-Out FIFO Buffer Memory DIP - DM9602 Bipolar-TTL Dual Retriggerable Resettable One Shots DIP 5 DM96L02 Bipolar-TTL Dual Retriggerable Resettable Monostable Multivibrator

ms-6535

Abstract: AA51 4116 lf 4116 16k ram 18-PIN BOX225012 TMS4132JDL 3as1 tms 375 CA31
Contextual Info: MOS LSI 32,768-BIT DYNAMIC RANDOM-ACCESS MEMORY i- 32,768 X — i- NOVEMBER 1978 1 Organization • 10% Tolerance on All Supplies All Inputs including Clocks TTL-Compatible 18-PIN SIDEBRAZE DUAL-IN-LINE PACKAGE TOP VIEW • Unlatched Three-State Fully TTL-Compatible

SR191

Abstract: DM77
Contextual Info: DM77/87SR191 National JtHmSemiconductor DM77/87SR191 2k x 8 16k-Bit Registered TTL PROM General Description The DM77/87SR191 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chlp. This device is organized as 2k words by 8

at28f020

Contextual Info: licensed Intel seconnsource CAT28F020 2 Megabit CMOS Flash Memory FEATURES • Commercial, Industrial and Automotive Temperature Ranges ■ Fast Read Access Time: 70/90/120 ns ■ Low Power CMOS Dissipation: - Active: 30 mA max CMOS/TTL levels - Standby: 1 mA max (TTL levels)

BD 9222

Abstract: SN7481 SN7484 SN7442 SN5481 WQ 5012 SN7444
Contextual Info: CIRCUIT TYPES SN5481, SN5484, SN7481, SN7484 16-BIT ACTIVE-ELEMENT MEMORIES TTL MSI SN5481/SN7481 CIRCUITS W FLAT PACKAGE TOP VIEW description The 16-bit active-element memory is a m o n o lith ic , high-speed, transistor-transistor-logic (TTL) X4 WRITE