TTL COUNTER Search Results

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

HLT28

Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

Contextual Info: >4M C C A COMPETITIVE EDGE The design of high speed TTL/CMOS systems is of­ ten made more challenging and more difficult than their ECL and GaAs counterparts due to the poor transmission line behavior of the TTL device inputs. Since inputs from either TTL or CMOS devices pro­

klt28

Abstract: MC10ELT28 HLT28
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

KLT28

Abstract: kt28 HLT28 HT28 MC100ELT28 MC10ELT28
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

Contextual Info: >4M CC A C O M PETITIVE EDGE The design of high speed TTL/CMOS systems is of­ ten made more challenging and more difficult than their ECL and GaAs counterparts due to the poor transmission line behavior of the TTL device inputs. Since inputs from either TTL or CMOS devices pro­

DM54ALS20AJ

Abstract: DM74ALS DM74ALS20AM DM74ALS20AN J14A M14A N14A TTL 74ALS
Contextual Info: DM54ALS20A/DM74ALS20A National Semiconductor Corporation DM54ALS20A/DM74ALS20A Dual 4-lnput NAND Gates Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

TTL LS 7400

Abstract: 74 LS 00 Logic Gates Advanced Schottky Family 4 bit barrel shifter LS 00 Logic Gates ls 7400 7400 ls 74lsxxx TTL 7400 LS TTL family characteristics
Contextual Info: Selection Information FAST/LS TTL FAST AND LS TTL 1 GENERAL INFORMATION TTL in Perspective FAST is manufactured on Motorola’s MOSAIC oxideisolated process.This process provides FAST with inherent speed/power advantages over the older junction-isolated 74S

DM54ALS21AJ

Abstract: DM74ALS DM74ALS21AN J14A M14A N14A
Contextual Info: DM54ALS21A/DM74ALS21A National Semiconductor Corporation DM54ALS21A/DM 74ALS21A Dual 4-Input AND Gates Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart

Contextual Info: December 1989 Semiconductor DM74ALS37A Quadruple 2-Input NAND Buffer Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with LS TTL counterpart Improved AC performance over LS37 Improved line receiving characteristics

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

MC10H605-D

Abstract: MC100H605 MC10H605 MC10H605FN
Contextual Info: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source

k 3555

Abstract: H607 MC100H607 MC10H607 MC10H607FN
Contextual Info: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive

MC100H605

Abstract: MC10H605 MC10H605FN
Contextual Info: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source

MC100H605

Abstract: MC10H605 MC10H605FN SOCKET PLCC28
Contextual Info: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source

Contextual Info: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive

Contextual Info: Semiconductor National DM74AS21 Dual 4-Input AND Gate General Description • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin for pin compatible with Schottky, low power Schottky, and advanced low power Schottky TTL counterpart

DM74AS810M

Contextual Info: ^W\ National Semiconductor DM74AS810 Quad 2-Input Exclusive-NOR Gate Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with advanced low power Schottky TTL counterpart Improved AC performance over advanced low power

TTL 74ALS

Abstract: 74ALS DM54ALS40AJ DM74ALS DM74ALS40AM DM74ALS40AN J14A LS40 M14A N14A
Contextual Info: DM54ALS40A/DM74ALS40A WJFM National /Z /m Semiconductor Corporation DM54ALS40A/DM74ALS40A Dual 4-Input NAND Buffers Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with LS TTL counterpart Improved AC performance over LS40

DM74ALS048

Abstract: DM54ALS04BJ DM74ALS DM74ALS04BM DM74ALS04BN J14A M14A N14A
Contextual Info: Corporation DM54ALS04B/DM74ALS04B Hex Inverters General Description Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart Improved AC performance over Schottky and low pow­