TRIPLE INPUT AND GATE PIN DIAGRAM Search Results

ScansU9X23

Contextual Info: F100101 Triple 5-Input OR/NOR Gate F100K ECL Product Description The F100101 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 k i l pull-down resistors and all outputs are buffered. Connection Diagrams 24-Pin DIP Top View Pin Names Dna, Dnb, Dnc

Contextual Info: £ÿj SCS-THOMSON T74LS15 TRIPLE 3-INPUT AND GATE DESCRIPTION The T74LS15 is a high speed TRIPLE 3-INPUT AND GATE with open collector output fabricated in LOW POWER SCHOTTKY technology. SCHEMATIC PIN CONNECTION (top view) DUAL IN LINE Open Collector Outputs

KK74HCT27A

Abstract: KK74HCT27AD KK74HCT27AN
Contextual Info: TECHNICAL DATA KK74HCT27A Triple 3-Input NOR Gate The KK74HCT27A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL LSTTL . The device provide the Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

74HCT27

Abstract: IZ74HCT27A 0751
Contextual Info: TECHNICAL DATA IN74HCT27A Triple 3-Input NOR Gate The IN74HCT27A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL LSTTL . The device provide the Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

74HC27

Abstract: IN74HC27A IN74HC27AD IN74HC27AN
Contextual Info: TECHNICAL DATA IN74HC27A Triple 3-Input NOR Gate The IN74HC27A is high-speed Si-gate CMOS device and are pin compatible with low power Schottky TTL LSTTL . The device provide Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

KK74HC27A

Abstract: KK74HC27AD KK74HC27AN
Contextual Info: TECHNICAL DATA KK74HC27A Triple 3-Input NOR Gate The KK74HC27A is high-speed Si-gate CMOS device and are pin compatible with low power Schottky TTL LSTTL . The device provide Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

74HC27

Abstract: IN74HC27A IN74HC27AD IN74HC27AN
Contextual Info: TECHNICAL DATA IN74HC27A Triple 3-Input NOR Gate The IN74HC27A is high-speed Si-gate CMOS device and are pin compatible with low power Schottky TTL LSTTL . The device provide Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

74HCT27

Abstract: IZ74HCT27A
Contextual Info: TECHNICAL DATA IN74HCT27A Triple 3-Input NOR Gate The IN74HCT27A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL LSTTL . The device provide the Triple 3-input NOR function. • Outputs Directly Interface to CMOS, NMOS, and TTL

F100K

Abstract: J24E W24B
Contextual Info: 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. n n n n 2000V ESD protection Pin/function compatible with 100101

Contextual Info: 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. n n n n 2000V ESD protection Pin/function compatible with 100101

Contextual Info: 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. n n n n 2000V ESD protection Pin/function compatible with 100101

F100K

Contextual Info: 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. n n n n n 2000V ESD protection Pin/function compatible with 100101

Contextual Info: 11 54F/74F11 Triple 3-Input AND Gate Connection Diagrams Pin Assignment for DIP and SOIC Pin Assignment for LCC and PCC Ordering Code: See Section 5 Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F U.L. HIGH/LOW Description Pin Names Inputs

Contextual Info: 11 54F/74F11 Triple 3-Input AND Gate Connection Diagrams Ordering Code: See Section 5 Pin Assignment for DIP and SOIC Pin Assignment for LCC and PCC Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F U.L. HIGH/LOW Description Pin Names Inputs

Contextual Info: 10 54F/74F10 Triple 3-Input NAND Gate Connection Diagrams Ordering Code: See Section 5 Pin Assignment for LCC and PCC Pin Assignment for DIP and SOIC Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F U.L. HIGH/LOW Description Pin Names Inputs

F100K

Abstract: J24E W24B
Contextual Info: Semiconductor 100301 Low Power Triple 5-Input OR/NOR Gate 2000V ESD protection General Description The 100301 is a m onolithic triple 5-input O R /N O R gate. All inputs have 50 k£l pull-dow n resistors and all outputs are buffered. Pin/function com patible w ith 100101

Contextual Info: AC11 54AC/74AC11 Triple 3-Input AND Gate Connection Diagrams 1Outputs Source/Sink 24 mA Ordering Code: See Section 6 Pin Assignment for LCC Pin Assignment or DIP, Flatpak and SOIC DC Characteristics (unless otherwise specified Symbol Parameter 54AC 74AC

Contextual Info: AC11 54AC/74AC11 Triple 3-Input AND Gate Connection Diagrams • Outputs Source/Sink 24 mA Ordering Code: See Section 6 Pin Assignment for DIP, Flatpak and SOIC Pin Assignment for LCC 5 DC Characteristics unless otherwise specified Parameter Symbol Icc Maximum Quiescent

Contextual Info: R C H II_ D E M IC O N D U C T Q R r 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 k£l pull-down resistors and all outputs are buffered. 2000V ESD protection Pin/function compatible with 100101

Contextual Info: Phifips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 3.6 V The 74L.V10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10.

DM74ALS11A

Abstract: 74ALS DM74ALS DM74ALS11AM DM74ALS11AN M14A N14A
Contextual Info: DM74ALS11A Triple 3-Input AND Gate General Description This device contains three independent gates, each of which performs the logic AND function. Features n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky

DM74ALS27

Abstract: 74ALS DM74ALS DM74ALS27M DM74ALS27N M14A N14A
Contextual Info: DM74ALS27 Triple 3-Input NOR Gate n Advanced oxide-isolated, ion-implanted Schottky TTL process n Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart n Improved AC performance over Schottky and low power Schottky counterparts

74ALS

Abstract: DM74ALS DM74ALS27 DM74ALS27M DM74ALS27N M14A N14A
Contextual Info: CM <9 National Semiconductor DM74ALS27 Triple 3-Input NOR Gate Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart Improved AC performance over Schottky and low pow­

Contextual Info: NATIONAL SEMICOND -CLOGIO □SQ'llSS QQbT13H 1 31E D DM54ALS10A/DM74ALS10A Triple 3-input NAND Gate • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart