TPCCL Search Results

563D

Abstract: 1h31 56m1 VSC9675
Contextual Info: 96& Scalable Architecture Framing Engine with M13 Data Book Revision 4.0 VITESSE SEMICONDUCTOR CORPORATION VSC9675 Scalable Architecture Framing Engine with M13 Overview Features 7 K H 9 6& LV DQ  FK DQ QHO 7- UDPHU ZLW K LQWHJUDWHG 0 WKDW SURYLGHV XS WR  FKDQQHOV RI '6

AT17C128

Abstract: AT17XXX AT6005 The AT6000 Series field programmable gate array guide
Contextual Info: AT6000 Series AT6000 Series Configuration Configuration is the process of loading a design into an AT6000 Series field programmable gate array FPGA . AT6000 Series devices are SRAM-based and can be configured any number of times. The entire device or select portions of a

LTC1100

Abstract: LTC1100ACS LTC1100AMJ LTC1100MJ
Contextual Info: 7"“ */V — ft-6 urm LINEAR TECHNOLOGY CORP S3E D TECHNOLOGY • 551fl4bû 0G0b533 13b H L T C LTC1100 Precision, Chopper Stabilized Instrumentation Amplifier F€flTUR€S D€SCRIPTIOf1 ■ Offset Voltage 1Ojj.V Max ■ Offset Voltage Drift 50nV/°C Max

synchronous inverter schematic ims 1600

Abstract: elcot tv kit circuit diagram iosq 050 pin diagram for IC cd 1619 cp in fm smd code transistor sd IL44 Z ET 439 IL44 transistor ksv3100a UTM ceramic RESISTOR 390 210-9
Contextual Info: CONFIGURABLE DESIGN PLD 1 S i 2 0 Regan Brampton, Tel: (4 1 6 Fax: (4 1 6 ) 9 • Si APPLICATION BOOK F P GA 9 LOGIC 4 Ì 4(I M A S S O C IA T E S Road, Unit 14 O ntario L 7 A 1C3 8 4 0 -6 0 6 6 8 4 0 -6 0 9 1 • GATE A R R A Y 1 9 9 5 iilmËL Atmel Programmable Logic Devices (PLDs)

AT17C128

Abstract: AT17XXX AT6005
Contextual Info: AT6000 Series AT6000 Series Configuration Configuration is the process of loading a design into an AT6000 Series field programmable gate array FPGA . AT6000 Series devices are SRAM-based and can be configured any number of times. The entire device or select portions of a

0.18-um CMOS technology length and width

Abstract: la 76938 TSMC 0.18 um CMOS library Jmpdma bidirectional shift register vhdl IEEE format 0.18-um CMOS technology characteristics tsmc cmos 0.18 um TSMC cmos 0.18um standard library TSMC cmos 0.18um 0.18-um SRAM
Contextual Info: VariCore Embedded Programmable Gate Array Core EPGA™ 0.18µm Family
Purpose VariCore™ IP blocks are embedded, reprogrammable “soft hardware” cores designed for use in ASIC and ASSP SoC applications. The first commercially available VariCore

AF23

Abstract: TR-303 VSC9670 VSC9680 TR-43801 0x860 djb1544
Contextual Info: VSC9670 Scalable Architecture Framing Engine for T1 Data Book Revision 4.0 VITESSE SEMICONDUCTOR CORPORATION VSC9670 Scalable Architecture Framing Engine for T1 Overview Features The Scalable Architecture Framing Engine forT1, the VSC9670, provides • A variety of loopbacks to DS1 or DS0

TSMC 0.18 um CMOS

Abstract: 0.18-um CMOS technology characteristics
Contextual Info: VariCore Embedded Programmable Gate Array Core EPGA™ 0.18 µm Family
Purpose VariCore™ IP blocks are embedded, reprogrammable “soft hardware” cores designed for use in ASIC and ASSP SoC applications. The first commercially available VariCore

AT6000 Series Configuration

Abstract: Application Notes 8078 microprocessor pin diagram AT17C128 AT17XXX AT6005
Contextual Info: AT6000 Series Configuration Configuration is the process of loading a design into an AT6000 Series Field Programmable Gate Array FPGA . AT6000 Series devices are SRAM-based and can be configured any number of times. The entire device or select portions of a

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds to 70 MHz Flip-Flop Toggle Rates to 250 MHz Symmetrical Architecture Thousands of Registers Flexible Busing Network Predictable Timing Delays 100% Factory-Tested Cache Logic Design

AD 4153

Abstract: AT17128 ad 8077 AT17XXX AT6002 AT6003 AT6005 AT6010 AT171 Vector Controls
Contextual Info: AT6000 Series AT6000 Series Configuration Configuration is the process of loading a design into an AT6000 Series field programmable gate array FPGA . AT6000 Series devices are SRAM-based and can be configured any number of times. The entire device or select portions of a design can be configured. Sections of the device can be configured while others continue to operate undisturbed.

Contextual Info: FIXED VOLTAGE REGULATOR NEGATIVE KA79MXX 3-TERMINAL 0.5A NEGATIVE V O LT A G E R EG U LA TO R S The KA79MXX series of 3-Term tnal medium current negative voltage regulators are monolithic Integrated circuits designed aa fixed voltage regulators. These regulators employ internal current limiting, thermal

T-703

Contextual Info: T emic U2010B S e m i c o n d u c t o r s Phase Control Circuit for Current Feedback Description d The U2010B is designed as a phase-control circuit in technolog It enables load-current detection and bipolar technology. has a soft-start function as well as reference voltage

scr25

Abstract: SCR PIN CONFIGURATION scr16 SCR30 AT94K AT94K05 AT94K10 AT94K40 atmel AT94K manual 12CCLK
Contextual Info: AT94K Series Configuration Configuration is the pr ocess by which a design is loaded into an AT94K Field Programmable System Level Integrated Circuit FPSLIC device. AT94K Series devices are SRAM based and can be configured any number of times. The entire

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds > 1 0 0 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns Input Delay 3.5 ns Output Delay Thousands of Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

atmel AT28C512

Abstract: AT17C010 AT17C128 AT17C256 AT17C512 AT17C65 AT40K AT40K05 AT40K10 AT40K20
Contextual Info: AT40K Series Configuration Configuration is the process by which a design is loaded into an AT40K series field programmable gate array FPGA . AT40K series devices are SRAM based and can be configured any number of times. The entire device or select portions can be configured. Sections can be configured while others continue to operate undisturbed. Full