TOP 201 YN Search Results

Contextual Info: SPECIFICATIONS MATERIAL AND FINISH: Contacts: Material: Brass Plating: Lead 10%Jin 90% Insulator: Material: Valox 420-SEO Rating: UL 94V-0 Mechanical: Mating Force: 4 kg max. Unmating Force: minimum: 1 kg maximum: 3.5 kg ELECTRICAL SPECIFICATIONS: Rated Current: 2A AC/1A DC

DC-001-A-CVSS

Contextual Info: D .C . P O W E R JA C K S * &• Power Dynamics D.C. Power Jacks nave a wide variety o t body styles ana mounting configurations with a large selection of pin diameters. Open ana closed frames are available PDI Power Dynamics, in c SPECIFICATIONS MATERIAL AND FINISH:

Contextual Info: EXAMPLE & ORDERING CODE •SUB CONNECTORS 1 SPECIFICATIONS MATERIAL AND FINISH: Material: Plating: Thickness: JIS G3141 SPCC-SD Equivalent to ANSI 1008 Tin Base Copper: 40p" Base Nickel: 40g" Tin: 120p" ELECTRICAL SPECIFICATIONS: Contacts: Material: Shell: .

Contextual Info: TELEPHONE JACKS & PLUGS Power Dynamics modular jacks and plugs are designed to meet a wide variety of telecommunication applications. They are available in F U l i RJ25 and RJ45 versions, Features include: shielding, various body styles, multiple ports and

Contextual Info: EXAMPLE & ORDERING CODE PC I R 36 B- CENTRONIC CONNECTORS CONNECTOR TYPE: UNFILTERED, SHIELDED = I = U metal face UNFILTERED, UNSHIELDED ( p l a s t ic f a c e ) NUMBER OF PINS: = 14 = 24 = 36 = 50 GENDER: PIN TYPE: MALE =s FEMALE =R RIGHT ANGLE SS BLANK

LT 7201

Abstract: AS221AF LT 7202
Contextual Info: SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA 256 x 9, 51 2 x 9, 1 024 x 9 AS YN CH RO N O US FIRST-IN, FIRST-OUT MEMORIES S C A S 221A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 • DV OR NP PACKAGE TOP VIEW R e a d s and Wr ites Can B e A s y n c h r o n o u s

Contextual Info: MDC-09 SERIES SNAP IN W ITH SHIELD CONTACT ARRANGEMENT P.C.B. LAYOUT TOP VIEW PART NO. MDC-093 □ !• 3 CONTACTS DIN CONNECTORS PART NO. MDC-094 |«—6.8— p PART NO. MDC-098 shownl 0 £ 2 ;3 H O L E S ^Q 5-5 0242; 3 HOLES 2.6-rt-Pi Phosphor Bronze Silver

LPR200JC10

Abstract: LPR200
Contextual Info: LPR200/201 D E V IC E S IN C O R P O R A T E D 16-bit Multilevel Pipeline Register DESCRIPTION FEATURES □ Pipeline Registers — Eight 16-bit High-Speed LPR200 or Seven 16-bit High-Speed with a Direct Feed-Through Path (LPR201 ) The LPR200 and LPR201 are program ­

Contextual Info: WTL 2010/WTL 2010A/WTL 201 OB PARALLEL ARRAY MULTIPLIER/ ACCUMULATOR July 1986 Features HIGH SPEED 45 ns commercial, worst case 55 ns military, worst case TW O’S COM PLEM ENT OR UNSIGNED M AGNITUDE INPUTS LOW POW ER CMOS W ITH TTL-COM PATIBLE I/O Icc = 100 m A max at 10 M Hz, Commercial

LM201

Abstract: ca301a LM301 replacement CA101 CA301H CA201 CA301 LM301A RCA-CA101 9C200
Contextual Info: Operational Amplifiers _ _ 0 3 0 _ _ <6% o CA101, CA201, CA301A, LM201*, LM301A* Operational Amplifiers F o r C o m m e rc ia l, In d u s tria l, a n d M ilita ry A p p lic a tio n s Features: • ■ ■ ■ S h o rt-c irc u it p ro te c tio n and la tch -fre e op eratio n

82p2

Contextual Info: jjjm ÆmSmmkjjjjjj jmSSm L8C201 /202/203/204 „ „ „ I mm MMMM 512/1K/2K/4K x 9-bit Asynchronous FIFO DEVICES INCORPORATED DESCRIPTION FEATURES □ First-In /First-O ut F IF O using D ual-Port M em ory □ A dvanced C M O S Technology □ H ig h Speed — to 10 ns Access Tim e

10AA022

Contextual Info: NF SERIES 1 .2 7 m m p itc h for CKBJw ptch fat md!b aio oaro-tc- ward co^a tir Right Angle Solder Dip Type Latch Header Plugs IORDERING CODE Part No. NFP— 10A—0 *1 2 NFP— 16A—0 *1 2 N P— 64A—01 2—BF ot terminal plating F = Gold Type of coniact plating B = Gold

Contextual Info: 4 T H IS D R A W IN G IS U N P U B L IS H E D . 3 RELEASED FO R P U B L IC A T IO N SEP 2 ,2 0 0 7 . REVISIO N S ALL RIGHTS RESERVED. COPYRIGHT 2007 LTR D E S C R IP TIO N KK R +0.05 R EVISED PER DATE E C R - 12 - 0 0 4 0 0 2 1ATE AND APVD c.\ 0 1 MAR2012

Contextual Info: ACS03MS fü HARRIS S E M I C O N D U C T O R Radiation Hardened Quad 2-Input NAND Gate with Open Drain January 1996 Features Pinouts Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96703 and Harris’ QM Plan

Contextual Info: H M 5 1 1 6 1 6 5 A S e r ie s Preliminary 1 ,0 4 8 ,576-w o rd x 16-blt D ynam ic R an d o m A c c e s s M em ory HITACHI The Hitachi HM5116165A is a CMOS dynamic RAM organized 1,048,576 words x 16 bits. It employs the most advanced CMOS technology for high perform ance and low pow er. The

ACS400

Contextual Info: UT54ACS4002/UT54ACTS4002 Radiation-Hardened Dual 4-Input NOR Gates FEATURES • 1.2^ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP

9G45

Abstract: 9P35 9G20 9T25 9D40 9T40 9T50 9p25 9T75 9D100
Contextual Info: LOW PROFILE D IG IT A L D E L A Y LKSIËS 14 PIN PACKAG E T T L COMPATIBLE S TAPS •SINGLE •DUAL •TRIPLE FOR MILITARY APPLICATIONS H E SERIES 9T,9G,9D AND 3P D I 303725? E S C 7 + t» .50 M AX, 3 + 4 + + + 12 11 + 13 ' 'v CORP 7 + o o + + 10 9 n + 14

V14241

Abstract: CY7C4201V CY7C4211V CY7C4231 CY7C4421 CY7C4421V 007h
Contextual Info: fax id: 5418 CY7C4421V/4201V/4211 V/4221 V PRELIMINARY CY7C4231 V/4241 V/4251 V ^ ;a a a z g g Æ? ri s a l i i J F ; U I F lm ß b ö Low Voltage 6 4 /2 5 6 /5 1 2 /1 K /2 K /4 K /8 K x 9 S ynchronous FIFOs Features • 32-pin PLC C H ig h-speed , low -pow er, first-in , firs t-o u t FIFO

Contextual Info: LINEAR INTEGRATED CIRCUITS 30-Lead DIP, See Diag. 536 NTE1800 TV Multiplex Sound Decoder, Vcc = 12VTyp G ND L im ite r A m p Input Filte r C ap n Filte r C ap 3 S AP Lam p B S te re o Lam p Q P hase C o m p C a p Q P hase C o m p C ap P hase C o m p Input

x1sv

Abstract: 1D10 850C SN74ALVCH16821
Contextual Info: SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037 -J U L Y 1995 DGG OR DL PACKAGE TOP VIEW • Member of the Texas Instruments Widebus Family • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • ESD Protection Exceeds 2000 V Per

TC4811F

Contextual Info: T O S H IB A C M O S D IG IT A L IN T E G R A T E D C IR C U IT I I " S IL IC O N M O N O L IT H IC • W 2 INPUT NAND GATE 2.8 - 0 . 3 -rO.2 1. 6 - 0.1 3 DC Supply Voltage - e SYMBOL RATING VDD VSS-0.5-VSS+20 V V VIN Vss-0-5-Vd d +O.5 Output Voltage VOUT

SD203 - 12

Abstract: SD202DC SD203 SD20 SD200CHP SD201 SD203DC SD2012 SD200
Contextual Info: TOPAZ SEMICONDUCTOR OSE I | l O S S E S t D O O l O O l a Q S D 2 0 0 ,S D 201 ' * 0 2 0 2 ,S D 2 0 3 S E M IC O N D U C T O R 7 ¿I - i ? N-CHAHNiL ENHANCEMENT-^ODE LATERAL D - M O S FETs O R D ER IN G IN FO R M ATIO N SD202DC SD203DC SD20ÛDC SD2Q1DC TO-52,4 Lead Pkg.

sy89429jc

Abstract: "Z3N" SY89429
Contextual Info: SYNERGY Clockworks PRELIMINARY SY89429 FREQUENCY SYNTHESIZER SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs ±25ps output jitter within 100 cycles Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface

IR10D

Abstract: RPS_PRES HY514264 R1799-2 TPI-10 74f04d 980b bergstik ARB12 mst12
Contextual Info: LXD980/980B Reference Design Schematics Reference Design Schematics Reference Design Schematic, Sheet 1:LXD 980 Top Level Schematic
 D-1 LXD980/980B Reference Design Users Guide Reference Design Schematic, Sheet 2:Raptor1 1 2 IR10DAT IR10CLK IR10ENA IR10DEN