TMS 320 C 6X PROCESSOR DATASHEET Search Results

TMS 320 C 6X processor

Contextual Info: PC755BM8 RISC Microprocessor Multichip Package Datasheet - Preliminary Specification Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz

PC755BM8

Abstract: MCP 67 MV PC745 PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

PC745

Abstract: PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

TMS 320 C 6X processor

Abstract: 2164A PC745 PC755M8 2164A dynamic ram cop interface l2-dp
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 300 MHz Maximum L2 Cache Frequency = 150 MHz Maximum 60x Bus Frequency = 66 MHz

cop interface

Abstract: PC745 PC755M8 PLL VCO MIL-PRF-38535 X755M
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

emcp

Abstract: JEDEC JESD51-8 BGA CI-CGA-255
Contextual Info: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support

TSPC603R

Abstract: microprocessor LNM80 DH21
Contextual Info: TSPC603R PowerPC 603e RISC Microprocessor Family PID7t-603e Datasheet Features • • • • • • • Superscalar 3 Instructions per Clock Peak Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support

Atmel - SAM3N ARM Cortex M3 Microcontroller

Abstract: Cortex A9 instruction set EEFC AT91SAM AT91SAM7S ISO7816 LQFP100 LQFP48 LQFP64 0x400E0A00
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 48 MHz – Thumb®-2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller Pin-to-pin compatible with AT91SAM7S legacy products 48- and 64-pin versions and

Atmel - SAM3N ARM Cortex M3 Microcontroller

Abstract: ATSAM3S Qtouch ATSAM3N2AA-AU Cortex A9 instruction set AT91SAM7S ISO7816 LQFP100 LQFP48 LQFP64
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 48 MHz – Thumb®-2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller Pin-to-pin compatible with AT91SAM7S legacy products 48- and 64-pin versions and

microprocessor

Abstract: G172
Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

0828H

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

BERG CONNECTOR

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

tag 8708

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

cortex a9

Abstract: ARM Cortex A8 arm cortex a9 cortex a9 core cortex a9 qfp Cortex A15 cortex a9 core processor architecture atmel SAM3S ATSAM3S2B cortex a15 core
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories

atmel SAM3S

Abstract: SAM3S4B sam3s bootloader atsam3s4a 6500DS
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S series (48- and 64-pin versions) Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

SAM3S

Abstract: atmel SAM3S sam3s4c atsam3s4c AT91SAM AT91SAM7S ISO7816 LQFP100 LQFP48 LQFP64
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories

SM320VC33

Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 D High-Performance Floating-Point Digital D Signal Processor DSP : - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS)

ATSAM3S2B

Abstract: SAM3S sam3s bootloader atsam3s4a ATSAM3S4 ATSAM3S Cortex A9 instruction set cortex a15 core sam3s4c ATSAM3S4BA-AU
Contextual Info: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories

cga motorola

Abstract: PCX755B IEC C13 pinout Tag 225 600 replacement PC745B PC755B MPC7400 PowerPC755B PC755 20d100
Contextual Info: Features H H H H H H H H H H H H H H H 18.1SPECint95, estimates 12.3 SPECfp95 @400Mhz PC755B 15.7SPECint95, 9SPECfp95 @350Mhz (PC745B) 733 MIPS @ 400Mhz (PC755B) et 641 MIPS@350Mhz (PC745B) Selectable bus clock (12 CPU bus dividers up to 10x) PD typical 6,4W @ 400Mhz, full operating conditions.

Mips 34k

Abstract: SM320VC33
Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 D High-Performance Floating-Point Digital D Signal Processor DSP : - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS)

SAM3S

Abstract: atsam3s4a
Contextual Info: AT91SAM ARM-based Flash MCU SAM3S SUMMARY Description Atmel's SAM3S series is a member of a family of 32-bit Flash microcontrollers based on the high performance ARM Cortex-M3 processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48

Contextual Info: Features • • • • • • • • • • • • • • • 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz TSPC750A with 1 MB L2 at 133 MHz 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A) 488 MIPS at 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x)

s23670w002

Abstract: DD 127 D TRANSISTOR cga motorola PC750A IN 750a t5 CBGA360 TSPC740A TSPC750A CI-CBGA360
Contextual Info: Features • • • • • • • • • • • • • • • 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz TSPC750A with 1 MB L2 at 133 MHz 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A) 488 MIPS at 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x)