TI OMAP 1610 Search Results

omap 1710

Abstract: OMAP 850 omap 1710 programming omap 1510 TI OMAP 1710 omap 1610 Spansion S29GL256N ti OMAP 850 CR10 CR14
Contextual Info: Interfacing Spansion Flash to TI OMAP Processors Application Note Introduction References • S29GL-N MirrorBit Flash Family Data Sheet, Publication Number S29GLN_00, Revision A, Amendment 7, Issue Date February 14, 2005. ■ S29WS-N MirrorBit Flash Family Data Sheet, Publication Number S29WSN_00, Rev G, Amendment 0, January 25, 2005.

omap1610

Abstract: SPRH199 omap1610 architecture ARM926 efuse ROM omap 1510 omap 1610 omap16 omap161x VIA ARM926
Contextual Info: Application Report SPRA919 - June 2003 Using Code Composer Studio with OMAP1610 Ki–Soo Lee Code Composer Studio Applications Engineering ABSTRACT Extending on the widely-adopted OMAP1510 processor, the more powerful OMAP1610 processor is a single-chip application processor that supports all cellular standards, and

Contextual Info: User's Guide SNVA231B – January 2008 – Revised April 2013 AN-1610 LP5552 Evaluation Board 1 LP5552 Overview The LP5552 is a PWI 2.0 compliant Energy Management Unit for reducing power consumption of standalone mobile phone processors such as baseband or applications processors.

circuit diagram wireless spy camera

Abstract: omap 1610 VLYNQ OMAP5912 irq94 SPRU754 ARM926EJS OMAP5910 IRQ45 IRQ59
Contextual Info: OMAP5912 Multimedia Processor Interrupts Reference Guide Literature Number: SPRU757A March 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

XTR105-DIE

Contextual Info: XTR105-DIE www.ti.com SBOS648 – AUGUST 2012 4-20mA CURRENT TRANSMITTER WITH SENSOR EXCITATION AND LINEARIZATION FEATURES 1 • • • • • • • • • APPLICATIONS Low Unadjusted Error Two Precision Current Sources Linearization 2- or 3-Wire RTD Operation

Contextual Info: OBSOLETE 100301 www.ti.com SNOS118B – AUGUST 1998 – REVISED APRIL 2013 100301 Low Power Triple 5-Input OR/NOR Gate Check for Samples: 100301 FEATURES DESCRIPTION • • • • The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all

MSP430G2252

Contextual Info: MSP430G2252-DIE www.ti.com SLAS853 – APRIL 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • 23 Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode 16-Bit RISC Architecture

Contextual Info: MSP430G2252-DIE www.ti.com SLAS853 – APRIL 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • 23 Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode 16-Bit RISC Architecture

Contextual Info: MSP430G2252-DIE www.ti.com SLAS853 – APRIL 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • 23 Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode 16-Bit RISC Architecture

Contextual Info: 100371 100371 Low Power Triple 4-Input Multiplexer with Enable Literature Number: SNOS433 100371 Low Power Triple 4-Input Multiplexer with Enable General Description The 100371 contains three 4-input multiplexers which share a common decoder inputs S0 and S1 . Output buffer gates

omap 1610

Contextual Info: OBSOLETE 100307 www.ti.com SNOS121A – OCTOBER 2009 – REVISED APRIL 2013 100307 Low Power Quint Exclusive OR/NOR Gate Check for Samples: 100307 FEATURES DESCRIPTION • • • • The 100307 is monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five

omap 1610

Contextual Info: OBSOLETE 100364 www.ti.com SNOS117B – AUGUST 1998 – REVISED APRIL 2013 100364 Low Power 16-Input Multiplexer Check for Samples: 100364 FEATURES DESCRIPTION • • • • The 100364 is a 16-input multiplexer. Data paths are controlled by four Select lines S0–S3 . Their decoding

Contextual Info: OBSOLETE 100304 www.ti.com SNOS120B – AUGUST 1998 – REVISED APRIL 2013 100304 Low Power Quint AND/NAND Gate Check for Samples: 100304 FEATURES DESCRIPTION • • • • The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate

omap 1610

Contextual Info: 100343 100343 Low Power 8-Bit Latch Literature Number: SNOS114 100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches, individual inputs, Dn , outputs (Qn), a common enable pin (E), and a latch enable pin (LE). A Q output follows its D input when both E and

TRF370417-DIE

Contextual Info: TRF370417-DIE www.ti.com SLWS242 – NOVEMBER 2013 QUADRATURE MODULATOR Check for Samples: TRF370417-DIE FEATURES 1 • • • APPLICATIONS Low Noise Floor Single Supply: 4.5-V–5.5-V Operation Silicon Germanium Technology • • • • • • • •

UC1825-DIE

Contextual Info: UC1825-DIE www.ti.com SLUSBO1 – JULY 2013 RAD-TOLERANT, HIGH-SPEED PWM CONTROLLER Check for Samples: UC1825-DIE FEATURES 1 • • • • • 1 Rad-Tolerant: 30 kRad (Si) TID (1) Compatible With Voltage- or Current-Mode Topologies Practical Operation Switching Frequencies

100352

Abstract: TI OMAP 1610
Contextual Info: 100352 100352 Low Power 8-Bit Buffer with Cut-Off Drivers Literature Number: SNOS112 100352 Low Power 8-Bit Buffer with Cut-Off Drivers General Description Features The 100352 contains an 8-bit buffer, individual inputs Dn , outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on

Contextual Info: 100363 100363 Low Power Dual 8-Input Multiplexer Literature Number: SNOS125 100363 Low Power Dual 8-Input Multiplexer General Description The 100363 is a dual 8-input multiplexer. The Data Select Sn inputs determine which bit (An and Bn) will be presented

CLGA

Abstract: ECL 100124
Contextual Info: OBSOLETE 100324 www.ti.com SNOS128B – AUGUST 1998 – REVISED APRIL 2013 100324 Low Power Hex TTL-to-ECL Translator Check for Samples: 100324 FEATURES DESCRIPTION • • • • • • • The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs

omap 1610

Contextual Info: OBSOLETE 100315 www.ti.com SNOS133B – AUGUST 1998 – REVISED APRIL 2013 100315 Low-Skew Quad Clock Driver Check for Samples: 100315 FEATURES DESCRIPTION • • • The 100315 contains four low skew differential drivers, designed for generation of multiple, minimum

Contextual Info: OBSOLETE 100314 www.ti.com SNOS115B – AUGUST 1998 – REVISED APRIL 2013 100314 Low Power Quint Differential Line Receiver Check for Samples: 100314 FEATURES DESCRIPTION • • • • The 100314 is a monolithic quint differential line receiver with emitter-follower outputs. An internal

Contextual Info: 100341 100341 Low Power 8-Bit Shift Register Literature Number: SNOS130 100341 Low Power 8-Bit Shift Register General Description Features The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup

Contextual Info: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible