Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
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IDT82V3011
TR62411
GR-1244-CORE
IDT82V3011
82V3011
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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PDF
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TR62411
GR-1244-CORE
IDT82V3012
DT82V3012
PVG56)
82V3012
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C155
Abstract: GR-1244-CORE IDT82V3155 TR62411
Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3155 FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks
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Original
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PDF
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IDT82V3155
TR62411
GR-1244-CORE
PVG56)
82V3155
C155
IDT82V3155
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GR-1244-CORE
Abstract: GR1244-CORE IDT82V3011 SSOP56 TR62411
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
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Original
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PDF
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IDT82V3011
TR62411
GR-1244-CORE
IDT82V3011
82V3011
GR1244-CORE
SSOP56
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C155
Abstract: GR-1244-CORE IDT82V3155 SSOP56 TR62411
Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3155 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3155
56-pin
TR62411
GR-1244-CORE
IDT82V3155
82V3155
C155
SSOP56
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GR-1244-CORE
Abstract: IDT82V3012 SSOP56 TR62411
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
56-pin
TR62411
GR-1244-CORE
IDT82V3012
82V3012
SSOP56
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GR-1244-CORE
Abstract: IDT82V3012 SSOP56 TR62411 tms 1944
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
56-pin
TR62411
GR-1244-CORE
PVG56)
82V3012
IDT82V3012
SSOP56
tms 1944
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
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Original
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PDF
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TR62411
GR-1244-CORE
IDT82V3011
IDT82V3011
PVG56)
82V3011
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
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Original
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PDF
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TR62411
GR-1244-CORE
IDT82V3011
IDT82V3011
82V3011
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Untitled
Abstract: No abstract text available
Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3155 FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks
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Original
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PDF
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IDT82V3155
TR62411
GR-1244-CORE
PVG56)
82V3155
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TR62411
Abstract: GR-1244-CORE GR1244-CORE IDT82V3011
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
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Original
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PDF
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TR62411
GR-1244-CORE
IDT82V3011
IDT82V3011
82V3011
GR1244-CORE
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IDT82V3011
Abstract: No abstract text available
Text: IDT82V3011 Data Sheet Change Notice Supplemental Information This notice describes the differences between the updated version and its previous version of the IDT82V3011 Data Sheet. It helps readers to identify the changes when the data sheet is upgraded.
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IDT82V3011
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IC-2354
Abstract: C155 GR-1244-CORE IDT82V3155 TR62411 82V3155
Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3155 FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks
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Original
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PDF
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IDT82V3155
TR62411
GR-1244-CORE
PVG56)
82V3155
IC-2354
C155
IDT82V3155
82V3155
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GR-1244-CORE
Abstract: IDT82V3012 SSOP56 TR62411
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
56-pin
TR62411
GR-1244-CORE
PVG56)
82V3012
IDT82V3012
SSOP56
|
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Untitled
Abstract: No abstract text available
Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3155 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3155
56-pin
TR62411
GR-1244-CORE
IDT82V3155
82V3155
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES PRELIMINARY IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.00625 ppm • Phase slope of 5 ns per 125 µs
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PDF
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TR62411
GR-1244-CORE
IDT82V3012
82V3012
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ns 332
Abstract: IDT82V3012
Text: IDT82V3012 Data Sheet Change Notice Supplemental Information This notice describes the differences between the updated version and its previous version of the IDT82V3012 Data Sheet. It helps readers to identify the changes when the data sheet is upgraded.
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IDT82V3012
F0312-03
tF16WL
tF16D
tF19D
tF32D
tF32WL
ns 332
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS IDT82V3010 FEATURES • • • • • • • • • • • • • • Supports AT&T TR62411 • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
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Original
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PDF
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IDT82V3010
TR62411
PVG56)
82V3010
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
56-pin
TR62411
GR-1244-CORE
PVG56)
82V3012
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F7C-2E3-20
Abstract: GR-1244-CORE IDT82V3012 TR62411
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES ADVANCE INFORMATION IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.00625 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
TR62411
GR-1244-CORE
IDT82V3012
82V3012
F7C-2E3-20
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GR-1244-CORE
Abstract: IDT82V3012 SSOP56 TR62411
Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs
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Original
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PDF
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IDT82V3012
56-pin
TR62411
GR-1244-CORE
IDT82V3012
82V3012
SSOP56
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GR-1244-CORE
Abstract: GR1244-CORE IDT82V3011 SSOP56 TR62411
Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
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Original
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PDF
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TR62411
GR-1244-CORE
IDT82V3011
PVG56)
82V3011
GR1244-CORE
IDT82V3011
SSOP56
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IDT82V3010
Abstract: SSOP56 TR62411 siemens Logo with analog input output
Text: T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS IDT82V3010 FEATURES • • • • • • • • • • • • • • Supports AT&T TR62411 • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
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Original
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PDF
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IDT82V3010
TR62411
PVG56)
82V3010
IDT82V3010
SSOP56
TR62411
siemens Logo with analog input output
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Untitled
Abstract: No abstract text available
Text: T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS IDT82V3010 FEATURES • • • • • • • • • • • • • • Supports AT&T TR62411 • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
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Original
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PDF
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IDT82V3010
TR62411
IDT82V3010
82V3010
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