TDCE Search Results

Contextual Info: SAFETY DRGANIZATIDNS RELIABILITY SPECIFICATIONS: TH IS F ILT E R HAS BEEN FORMALLY RRCDONIZOD, C ER TIFIED DR APPROVED BY THE LIST ED AGENCY, THEREFORE, ALL TEST/REQUIREMENTS SP EC IFIED IN THE LATEST REVISION OF TBE FOLLOWING AGENLY STANDARDS HAVE BEEN MET

CY8C38

Abstract: CY8C3866 Cypress touch panel BOSCH CONNECTOR CATALOG CY8C3866LTI-068 CY8C3866PVI-070 CY8C3866AXI-039
Contextual Info: PSoC 3: CY8C38 Family Datasheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal

CY8C3665

Abstract: 8051 8bit microcontroller cy8c3665lti-006
Contextual Info: PSoC 3: CY8C36 Family Data Sheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal

CY7C161

Abstract: CY7C162 C1624
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

7cl6

Abstract: D-2501 CY7C161A CY7C162 CY7C162A
Contextual Info: CYPRESS SEMICONDUCTOR 4bE » B SSfl'lbfe.S □ QQbMSb b q c y p CY7C161A CY7C162A • - j/ "— = 16,384 x 4 Static RAV RAM Separate I/O SEMICONDUCTOR Features • Automatic power-down when dese­ lected • Transparent write 7C161A • CMOS for optimum speed/power

CY7C101A

Abstract: CY7C102A 7C101A-12 l3lx
Contextual Info: PRELIMINARY 9 / C Y PR E SS CY7C101A CY7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C101A and CY7C102A are high­ perform ance CMOS static RAM s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac­

T801

Abstract: speedo meter N10E inmos transputer T800 TIN30 T800 transputer T801-20 2AF3 w188
Contextual Info: 127 IMS T801 transputer □ Preliminary Data FEATURES 32 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate 4.3 Mflops (peak) instruction rate Debugging support 64 bit on-chip floating point unit which conforms to IEEE 754 4 Kbytes on-chip static RAM

Color Filter Array CFA

Contextual Info: LM98501 LM98501 10-Bit, 27 MSPS Camera Signal Processor Literature Number: SNAS053B October 6, 2011 LM98501 10-Bit, 27 MSPS Camera Signal Processor General Description Features The LM98501 is a CCD signal processor for electronic cameras. The processor provides a common interface to a number of different image sensors including CCD, CMOS, and

8051 microcontroller based Solar Charge Controller

Contextual Info: PSoC 3: CY8C34 Family Data Sheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal

Contextual Info: PSoC 3: CY8C34 Automotive Family Datasheet Programmable System-on-Chip PSoC® General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C34 family offers a modern method

Z- FIO

Abstract: dcp 4 z Z8038
Contextual Info: Z I L O G INC 17E D T1ÖM043 DD1E0Ô3 T " T -S £ -3 3 -D 3 Z8038/Z8538 FIO FIFO Input/ Output Interface Unit October 1988 Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte

SMD45

Abstract: SMD34 224 d5 smd zd 15 p240f1 SMD52 SMD46 SMD-42 smd M16 SMD23
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

8051 microcontroller based Solar Charge Controller

Contextual Info: PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip PSoC® General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal

HD61830A00

Abstract: hd61830B00 LCD Controller HD61830 HD61830 HD6303 HM6116 HD61830B HD61830B00H marking db2 V6 marking code diode
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

C1623

Abstract: C1624 c162 c1627 C1622 CY7C161 CY7C162 C1628 C1625
Contextual Info: 1CY 7C16 2 CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

Contextual Info: Target Spec 128M DDR SDRAM K4D263238E-GC 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 0.2 January 2003 Samsung Electronics reserves the right to change products or specification without notice.

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

74F74

Abstract: inmos transputer T225 transputer Inmos t805 FP 8022 74F04 800E 801C T222 T225
Contextual Info: IMS T225 16-bit transputer FEATURES H 16 bit architecture H 33 ns internal cycle time H 30 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 60 Mbytes/sec sustained data rate to internal memory H 64 Kbytes directly addressable external memory

Contextual Info: mw CYPRESS Features • High speed — 20 ns tAA • CMOS Tor optim um speed/power • T ran sp aren t write 7C161A • Low active power — 550 mW • Low standby power — 220 mW • TTL-com patible inputs and outputs • Automatic power-down when dese­

Contextual Info: CY7C161 CY7C162 16Kx 4 Static RAM with Separate I/O Features into the memory location specified on the address pins Ao through A13 . Reading the device is accomplished by tak­ ing the chip enables (CEi, CE2) LOW while write enable (WE) remains HIGH. Under these conditions the contents of the

Contextual Info: 256M GDDR3 SDRAM K4J55323QG 256Mbit GDDR3 SDRAM Revision 1.2 March 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

timing controller SHART

Abstract: T21N K4U52324Q SAMSUNG GDDR4 K4U52324QE-BC09 GDDR4
Contextual Info: 512M GDDR4 SGRAM K4U52324QE 512Mbit GDDR4 SGRAM 2M x 32Bit x 8 Banks Graphic Double Data Rate 4 Synchronous DRAM with Uni-directional Data Strobe and DLL 136Ball FBGA Revision 1.0 June 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

K4D263238G-VC33

Contextual Info: 128M GDDR SDRAM K4D263238G-GC 128Mbit GDDR SDRAM 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.7 February 2005 Samsung Electronics reserves the right to change products or specification without notice.

K4J10324KE-HC1A

Abstract: K4J10324KE-HC14 T21N K4J10324KE k4j10324 K4J10324KE-HC12
Contextual Info: Target 1Gb GDDR3 SDRAM K4J10324KE 1Gbit GDDR3 SDRAM 136FBGA with Halogen-Free & Lead-Free RoHS compliant Revision 0.1 December 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,