IS42VS16100E
Abstract: 42VS16100E IS42VS16100E-75BLI
Text: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11
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IS42VS16100E
4000-mil
60-ball
400-mil
IS42VS16100E
42VS16100E
IS42VS16100E-75BLI
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Untitled
Abstract: No abstract text available
Text: iPEM 2.4 Gb SDRAM-DDR2 AS4DDR232M72PBG 32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Grid Array PBGA , 25 x 32mm
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AS4DDR232M72PBG
32Mx72
AS4DDR232M72PBG
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f11u
Abstract: FC 0012 TSOP 50 PIN cs-7sa CS7SA k0219 EN5055
Text: Ordering number : EN5055 _ CMOS LSI No. 5055 LC382161T-17 IS ipîppi; 2 MEG 65536 words x 16 bits x 2 banks Synchronous DRAM J 8¡|lí¡Bí: 1 Overview Package Dimensions The LC382161 series products are 3.3 V single-voltage power supply synchronous DRAMs with a 65536-word x
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EN5055
LC382161T-17
LC382161
65536-word
16-bit
50-pin
f11u
FC 0012
TSOP 50 PIN
cs-7sa
CS7SA
k0219
EN5055
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PDF
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RT3PE600L
Abstract: RT3PE3000L AES-128 PAC10 LG484 ProASICPLUS Flash Family FPGAs Advanced v0.1
Text: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging
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MIL-STD-883
RT3PE600L
RT3PE3000L
AES-128
PAC10
LG484
ProASICPLUS Flash Family FPGAs Advanced v0.1
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PDF
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SA6954
Abstract: S29WS064N S29WS128N S29WS256N WS128N FFC00
Text: S29WSxxxN MirrorBit Flash Family S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit 16/8/4 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory PRELIMINARY Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.70 to
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S29WSxxxN
S29WS256N,
S29WS128N,
S29WS064N
16-Bit)
SA6954
S29WS064N
S29WS128N
S29WS256N
WS128N
FFC00
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Advanced Boot Block Flash
Abstract: AES-128 CS201 CS281 CS289 AGLP125
Text: v1.5 IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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130-nm,
Advanced Boot Block Flash
AES-128
CS201
CS281
CS289
AGLP125
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PDF
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A3P600
Abstract: A3P060 A3P1000 A3P125 A3P250 AECQ100 AEC-Q100 FG144 FG256 FG484
Text: v1.0 Automotive ProASIC3 Flash Family FPGAs Features and Benefits Low Power • 1.5 V Core Voltage • Support for 1.5-V-Only Systems • Low-Impedance Flash Switches High-Temperature AEC-Q100–Qualified Devices • Grade 2 105°C TA 115°C TJ • Grade 1 125°C TA (135°C TJ)
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AEC-Q100
A3P600
A3P060
A3P1000
A3P125
A3P250
AECQ100
FG144
FG256
FG484
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PDF
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A3PE3000L FG484
Abstract: Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y
Text: v1.3 ProASIC3L Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for
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130-nm,
A3PE3000L FG484
Actel pdf on radio emitter
A3PE3000L
FG144
FG256
FG324
FG484
PQ208
TDP 245 Y
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PDF
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QN68
Abstract: VQ100 actel part markings
Text: Advance v0.4 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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130-nm,
128-Bit
QN68
VQ100
actel part markings
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PDF
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GTL33
Abstract: CAT16-LV4F12 PAC10 JESD8-12A
Text: 2 – IGLOOe DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA
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AFS600-FG256
Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
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130-nm,
128-Bit
AFS600-FG256
zo 103 ma 75 607
A54 ZENER
flashpro3 schematic
mark AT0
Unipolar PC atx 400 P4 power supply diagram
zener Diode B23
PQ208
QN108
QN180
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PDF
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IS42S16400L
Abstract: No abstract text available
Text: ISSI IS42S16400L 1 Meg Bits x 16 Bits x 4 Banks 64-MBIT SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 166, 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge PRELIMINARY
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IS42S16400L
64-MBIT)
IS42S16400L
16-bit
54-Pin
IS42S16400L-6T
400-mil
IS42S16400L-7T
IS42S16400L-10T
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LM 8002
Abstract: amz8000 Z8001 crystal OSCILATOR 4mhz Z8000 Z8002 AmZ8
Text: i Am8127 < AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Four TTL-level clocks G enerates synchronized TTL com patible clocks at 16MHz, 2M Hz and 1MHz to drive memory circuits and LSI peripheral devices. An additional TTL clock is synchronized with the CPU high-level clock for
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Am8127
AmZ8000
16MHz,
Am8127
03432C
WF002010
LM 8002
Z8001
crystal OSCILATOR 4mhz
Z8000
Z8002
AmZ8
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PDF
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Untitled
Abstract: No abstract text available
Text: Revision 22 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode
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Untitled
Abstract: No abstract text available
Text: IBM13Q8734HCA 8M X 72 Registered SDRAM Module Features • 200-P in JE D E C Standard, R egistered 8-B yte Dual In-line M em ory M odule • A utom atic and controlled P recharge C om m ands • Program m able O peration: • 8M x 72 S ynchronous DRAM DIMM
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IBM13Q8734HCA
200-P
IBM13Q8734H
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PDF
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mJI 1032
Abstract: T522 capacitor TSOP 50 PIN ULN 232 V11J LC382161T-17 TSOP50 5B60
Text: Ordering number: EN5055 CMOS LSI LC382161T-17 No. 5065 SA\YO 2 MEG 65536 words x 16 bits x 2 banks Synchronous DRAM Overview Package Dimensions The LC382161 series products are 3.3 V single-voltage power supply synchronous DRAMs with a 65536-word x 16-bit x 2-bank organization. These DRAMs feature a
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EN5055
LC382161T-17
LC382161
65536-word
16-bit
50-pin
c17G7b
0D15317
mJI 1032
T522 capacitor
TSOP 50 PIN
ULN 232
V11J
LC382161T-17
TSOP50
5B60
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PDF
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CAT16-LV4F12
Abstract: PAC10 RAM512X18
Text: 2 – ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA
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QN68
Abstract: VQ100 PAC11 ProASIC3 handbook
Text: Advance v0.5 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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Original
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130-nm,
128-Bit
QN68
VQ100
PAC11
ProASIC3 handbook
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PDF
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AES-128
Abstract: FG256 FG484
Text: v2.0 IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power
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130-nm,
AES-128
FG256
FG484
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PDF
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A54 ZENER
Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Text: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents
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128-Bit
130-nm,
A54 ZENER
AFS600-FG256
mark AT0
QN108
CORE8051
bipolar ROM
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PDF
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JESD21-C
Abstract: E8870DH JESD79 mrf 245 E8870 JESD-21C 567-Ball
Text: Intel 82870DH DDR Memory Hub DMH Datasheet Product Features • ■ ■ ■ ■ Two independent DDR DIMM channels per DMH. — 4 DIMMs per DDR Channel. — Registered PC1600 DDR DIMMs. Write Buffers to minimize large turnaround times. Pass through architecture for Read and
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82870DH
PC1600
Tunnels88
E8870DH
JESD21-C
JESD79
mrf 245
E8870
JESD-21C
567-Ball
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PDF
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IS42R32200C1
Abstract: No abstract text available
Text: ISSI IS42R32200C1 512K Bits x 32 Bits x 4 Banks 64-MBIT SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 2.5V power supply
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IS42R32200C1
64-MBIT)
IS42R32200C1
32-bit
86-Pin
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PDF
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RAM32M
Abstract: RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 RAM64M ROM64x1 XC6VLX75T ROM256x1
Text: Virtex-6 FPGA Configurable Logic Block User Guide Virtex-6 FPGA CLB [optional] UG364 v1.1 September 16, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
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UG364
RAM32M
RAM64X1D
SRLC32E
RAM128X1D
RAM256X1S
SRL32
RAM64M
ROM64x1
XC6VLX75T
ROM256x1
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY INFORMATION L9D222G72BG3 2.2 Gb, DDR2, 32 M x 72 Integrated Module IMOD Benefits FEATURES DDR2 SDRAM Data Rate = 800,667,533 and 400Mbps Available in INDUSTRIAL, EXTENDED and MIL-TEMP Package: 16mm x 22mm – 208PBGA, 1.00mm pitch Differential Data Strobe (DQS, DQSx\) per byte
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L9D222G72BG3
400Mbps
208PBGA,
LDS-L9D222G72BG3-B
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PDF
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